Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65 nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs due to the interaction between CoWP and etch plasma during SiCN opening step leading to lower line resistance compared to SiCN reference. Furthermore, wet cleaning after patterning step must be carefully processed in order to remove residues while keeping CoWP integrity. Electrical and reliability performance show that a clean recipe can be efficient to remove residues leading to low via resistance but in the same time, no electromigration improvement compared to SiCN reference is observed due to CoWP degradation and vice versa. To overcome integration issues, a new integration scheme called hybrid punch through (HPT) approach is proposed. In this approach, the patterning step is modified by SiCN open removal and it is followed by an adapted punch through process during metallization to open the via. HPT approach allows avoiding contact between CoWP and etch plasma or cleaning chemistry and leads to better electrical performance in terms of via and line resistances compared to standard scheme without degrading CoWP.