E-resources
Peer reviewed
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Romanjek, K.; Augendre, E.; Van Den Daele, W.; Grandchamp, B.; Sanchez, L.; Le Royer, C.; Hartmann, J.-M.; Ghyselen, B.; Guiot, E.; Bourdelle, K.; Cristoloveanu, S.; Boulanger, F.; Clavelier, L.
Microelectronic engineering, 07/2009, Volume: 86, Issue: 7Journal Article, Conference Proceeding
The origin of parasitic leakage that occurs in some GeOI pMOSFETs has been investigated and located at the Ge-buried oxide (BOX) interface. Silicon passivation of that interface was found to be effective in reducing this current. An optimum thickness of the buried silicon capping is required to reduce the parasitic leakage current while preserving Ge-like back channel transport properties.
