The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to compensate for pre-cursor inter-symbol interference (ISI) without affecting the impedance matching achieved by ZQ calibration. This phase equalization is implemented by minimizing hardware to overcome the design complexity of conventional phase equalization and reduce power consumption. The prototype chip is fabricated in the 65-nm CMOS process. The transmitter and the ZQ calibration scheme occupy an area of 0.074 and 0.041 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>, respectively. The proposed ZQ calibration achieves a maximum error rate of 1.5% and an average error rate of 0.7%. In addition, the transmitter achieves an energy efficiency of 1.145 pJ/bit and an FoM of 0.11 pJ/bit/(dB/pin) at 12 Gb/s.