UNI-MB - logo
UMNIK - logo
 
E-resources
Full text
Peer reviewed Open access
  • Metasurface‐Programmable Wi...
    F. Imani, Mohammadreza; Abadal, Sergi; del Hougne, Philipp

    Advanced science, 09/2022, Volume: 9, Issue: 26
    Journal Article

    This paper introduces the concept of smart radio environments, currently intensely studied for wireless communication in metasurface‐programmable meter‐scaled environments (e.g., inside rooms), on the chip scale. Wireless networks‐on‐chips (WNoCs) are a candidate technology to improve inter‐core communication on chips but current proposals are plagued by a dilemma: either the received signal is weak, or it is significantly reverberated such that the on–off‐keying modulation speed must be throttled. Here, this vexing problem is overcome by endowing the wireless on‐chip environment with in situ programmability which enables the shaping of the channel impulse response (CIR); thereby, a pulse‐like CIR shape can be imposed despite strong multipath propagation and without entailing a reduced received signal strength. First, a programmable metasurface suitable for integration in the on‐chip environment (“on‐chip reconfigurable intelligent surface”) is designed and characterized. Second, its configuration is optimized to equalize selected wireless on‐chip channels “over the air.” Third, by conducting a rigorous communication analysis, the feasibility of significantly higher modulation speeds with shaped CIRs is evidenced. The results introduce a programmability paradigm to WNoCs which boosts their competitiveness as complementary on‐chip interconnect solution. A programmable metasurface is included inside a chip package, and suitable metasurface configurations are identified that equalize wireless channels on the chip over‐the‐air to mitigate inter‐symbol interference. The largely improved data transfer rates boost the competitiveness of wireless networks‐on‐chips (WNoCs) as complementary interconnect technology. WNoCs aim to avert the risk of communication‐limited performance of multicore chips.