This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in ...a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- ¿m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm 2 . With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.
A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of ...the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.
This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in ...a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- mu hbox m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 , times , 0.45 hbox mm 2 . With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be - 126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The ...VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3ps rms .
Reverse shoulder arthroplasty (RSA) is frequently performed in the revision setting as a salvage procedure. The purpose of this study was to report the clinical outcomes and complication, ...reoperation, and revision rates after revision RSA (RRSA) stratified according to the primary shoulder procedure undergoing revision.
Four databases (Embase, MEDLINE, SPORTDiscus, and Cochrane Controlled Trials Register) were searched for eligible studies published between January 1985 and September 2017. The primary outcomes of interest included pain, active range of motion, and functional outcome scores. Secondary outcomes included complication, reoperation, and revision rates.
A total of 43 studies (1041 shoulder arthroplasties) met the inclusion criteria, with a mean follow-up period of 43.8 months (range, 31.1-57.2 months). Pain scores improved in all groups; however, none reached statistical significance. Range of motion improved in all groups, except for external rotation in the RSA category. RRSA demonstrated significant improvements in the Simple Shoulder Test score and Constant score (CS) in the group undergoing hemiarthroplasty (HA) for fracture, CS in the group undergoing HA for other indications, and CS in the group undergoing anatomic total shoulder arthroplasty. Pooled complication rates were highest in the failed RSA group (56.2%), followed by the group undergoing HA for other indications (27.7%), total shoulder arthroplasty group (23.6%), soft-tissue repair group (20.6%), open reduction and internal fixation group (19.0%), and group undergoing HA for fracture (13.6%).
Compared with other revision indications, RRSA for failed HA demonstrated the most favorable outcomes, whereas the highest complication and revision rates were observed in the RSA subgroup. This information is useful when establishing patient expectations regarding the risks, benefits, and complication and revision rates of RRSA.
Two 60 GHz power amplifiers are presented in standard 90 nm CMOS using integrated power combining and matching networks. The power amplifiers incorporate 4-way/2-way power splitters and combiners ...into their matching networks rather than using separate structures, and achieve 1 dB output power of 12.1/10.1 dBm and saturation output power of 14.2/11.6 dBm respectively with saturation efficiency of 18.1/17.7% respectively when operated with a 1 V supply.
... to what happens in a classical PLL, the PD/CP noise is not multiplied by Formula Omitted in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. ... no frequency divider ...is needed in the locked state and hence divider noise and power can be eliminated.
30 GHz CMOS Low Noise Amplifier Adabi, E.; Heydari, B.; Bohsali, M. ...
2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,
2007-June
Conference Proceeding
30 GHz low noise amplifier was designed and fabricated in a 90nm digital CMOS process. The mm-wave amplifier has a peak gain of 20 dB at 28.5 GHz and a 3dB bandwidth of 2.6 GHz with the input and ...output matching better than 12 dB and 17 dB over the entire band respectively. The NF is 2.9 dB at 28 GHz and less than 4.2 dB across the band and it can deliver 2 dBm of power to a matched load at its 1 dB compression point. The amplifier has a measured linearity of IIIP3= -7.5 dBm. It consumes 16.25 mW of power using a low supply voltage of 1 V and occupies an area (excluding the pads) of 1600 μ m x 420 μ m.
A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the ...sampler to the VCO. The 2.2GHz PLL in 0.18¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.
A two-stage 60 GHz 90 nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output ...power. The measured P -1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.
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