All 2-terminal non-volatile memory devices based on
resistance switching
are
memristors
, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive ...“fingerprint” characterized by a
pinched hysteresis loop
confined to the first and the third quadrants of the
v
–
i
plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this
tutorial
to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that
spin-transfer magnetic tunnel junctions
are examples of memristors. We have also demonstrated that both
bipolar
and
unipolar
resistance switching devices are memristors.
The goal of this
tutorial
is to introduce some fundamental circuit-theoretic concepts and properties of the memristor that are relevant to the analysis and design of
non-volatile
nano memories where binary bits are stored as resistances manifested by the memristor’s continuum of equilibrium states. Simple pedagogical examples will be used to illustrate, clarify, and demystify various misconceptions among the uninitiated.
Neuromorphic computing (NC) is a new generation of artificial intelligence. Memristors are promising candidates for NC owing to the feasibility of their ultrahigh‐density 3D integration and their ...ultralow energy consumption. Compared to traditional electrical memristors, the emerging optoelectronic memristors are more attractive owing to their ability to combine the advantages of both photonics and electronics. However, the inability to reversibly tune the memconductance with light has severely restricted the development of optoelectronic NC. Here, an all‐optically controlled (AOC) analog memristor is realized, with memconductance that is reversibly tunable over a continuous range by varying only the wavelength of the controlling light. The device is based on the relatively mature semiconductor material InGaZnO and a memconductance tuning mechanism of light‐induced electron trapping and detrapping. It is found that the light‐induced multiple memconductance states are nonvolatile. Furthermore, spike‐timing‐dependent plasticity learning can be mimicked in this AOC memristor, indicating its potential applications in AOC spiking neural networks for highly efficient optoelectronic NC.
An all‐optically controlled (AOC) analog memristor is realized based on the relatively mature material InGaZnO. The memconductance is reversibly tunable over a continuous range by varying only the wavelength of the controlling light. This device has promising applications in AOC spiking neural networks for highly efficient optoelectronic neuromorphic computing.
Three Fingerprints of Memristor Adhikari, Shyam Prasad; Sah, Maheshwar Pd; Hyongsuk Kim ...
IEEE transactions on circuits and systems. I, Regular papers,
11/2013, Letnik:
60, Številka:
11
Journal Article
Recenzirano
This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a "pinched ...hysteresis loop" in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.
As the limits of transistor technology are approached, feature size in integrated circuit transistors has been reduced very near to the minimum physically-realizable channel length, and it has become ...increasingly difficult to meet expectations outlined by Moore's law. As one of the most promising devices to replace transistors, memristors have many excellent properties that can be leveraged to develop new types of neural and non-von Neumann computing systems, which are expected to revolutionize information-processing technology. This survey provides a comparative overview of research progress on memristors. Different memristor synaptic devices are classified according to stimulation patterns and the working mechanisms of these various synaptic devices are analyzed in detail. Crossbar-based memristors have demonstrated advantages in physically executing vector-matrix multiplication and enabling highly power-efficient and area-efficient neuromorphic system designs. The extensive uses of crossbar-based memristors cover in-memory logic, vector-matrix multiplication, and many other fundamental computing operations. Furthermore, memristor-based architectures for efficient neural network training and inference have been studied. However, memristors have non-ideal properties due to programming inaccuracies and device imperfections from fabrication, which lead to error or mismatch in computed results. To build reliable memristor-based designs, circuit-level, algorithm-level, and system-level solutions to memristor reliability issues are being studied. To this end, state-of-the-art realizations of memristor crossbars, crossbar-based designs, and peripheral circuitry are presented, which show both promising full-system inference accuracy and excellent power efficiency in multiple tasks. Memristor in-situ learning benefits from high energy efficiency and biologically-imitative characteristics, which are conducive to further realizing hardware acceleration of cognitive learning. At present, the learning and training processes of brain-like networks are complex, presenting great challenges for network design and implementation.
This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of ...each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map, is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images.
Memristor crossbar arrays are used in a wide range of in-memory and neuromorphic computing applications. However, memristor devices suffer from non-idealities that result in the variability of ...conductive states, making programming them to a desired analog conductance value extremely difficult as the device ages. In theory, memristors can be a nonlinear programmable analog resistor with memory properties that can take infinite resistive states. In practice, such memristors are hard to make, and in a crossbar, it is confined to a limited set of stable conductance values. The number of conductance levels available for a node in the crossbar is defined as the crossbar's resolution. This paper presents a technique to improve the resolution by building a super-resolution memristor crossbar with nodes having multiple memristors to generate <inline-formula> <tex-math notation="LaTeX">r </tex-math></inline-formula>-simplicial sequence of unique conductance values. The wider the range and number of conductance values, the higher the crossbar's resolution. This is particularly useful in building analog neural network (ANN) layers, which are proven to be one of the go-to approaches for forming a neural network layer in implementing neuromorphic computations.
If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates ...as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing the DRM technique to second-order systems, is applied to the models of Memristor CNN (M-CNN) cells, accomodating dynamic memristors. This allows to gain insights into the operating principles of these cellular structures, which make computations through the evolution of their states toward prescribed equilibria. Our analysis uncovers all possible local and global phenomena, which may emerge in the cell phase space under zero offset current for any self-feedback synaptic weight. Under these hypotheses, the dynamics of the M-CNN cell may significantly differ from those of a standard space-invariant CNN counterpart. The insertion of an offset current into each cell endows it with further properties, including monostability. The analysis method is used to demonstrate how a non-autonomous memristive array exploits the capability of its cells to feature monostability or bistability, depending upon the respective offset currents, to compute the element-wise logical AND between two binary images.
Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with ...memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.
Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves ...one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.
Local activity is the capability of a system to amplify infinitesimal fluctuations in energy. Complex phenomena, including the generation of action potentials in neuronal axon membranes, may never ...emerge in an open system unless some of its constitutive elements operate in a locally active regime. As a result, the recent discovery of solid-state volatile memory devices, which, biased through appropriate DC sources, may enter a local activity domain, and, most importantly, the associated stable yet excitable sub-domain, referred to as edge of chaos, which is where the seed of complexity is actually planted, is of great appeal to the neuromorphic engineering community. This paper applies fundamentals from the theory of local activity to an accurate model of a niobium oxide volatile resistance switching memory to derive the conditions necessary to bias the device in the local activity regime. This allows to partition the entire design parameter space into three domains, where the threshold switch is locally passive (LP), locally active but unstable, and both locally active and stable, respectively. The final part of the article is devoted to point out the extent by which the response of the volatile memristor to quasi-static excitations may differ from its dynamics under DC stress. Reporting experimental measurements, which validate the theoretical predictions, this work clearly demonstrates how invaluable is non-linear system theory for the acquirement of a comprehensive picture of the dynamics of highly non-linear devices, which is an essential prerequisite for a conscious and systematic approach to the design of robust neuromorphic electronics. Given that, as recently proved, the potassium and sodium ion channels in biological axon membranes are locally active memristors, the physical realization of novel artificial neural networks, capable to reproduce the functionalities of the human brain more closely than state-of-the-art purely CMOS hardware architectures, should not leave aside the adoption of resistance switching memories, which, under the appropriate provision of energy, are capable to amplify the small signal, such as the niobium dioxide micro-scale device from NaMLab, chosen as object of theoretical and experimental study in this work.
PDF
