This work investigates a low-temperature and high-pressure (LTHP) hydrogen treatment in Si-channel and SiGe-channel metal-oxide-semiconductor capacitors (MOSCAPs). The LTHP hydrogen treatment can ...repair dangling bonds in the SiO 2 /Si and SiO 2 /SiGe interfaces to enhance device performance. Additional parameters of the treatment, including treatment pressure and time, are also investigated to better understand the reaction mechanisms, which further proves the effectiveness and potential of this supercritical fluid (SCF)-based treatment. In addition, this treatment will not damage the front structure and materials due to the relatively low process temperature (120 °C). Therefore, this treatment can be a nondestructive postannealing process. The results of extracting interface defect density (<inline-formula> <tex-math notation="LaTeX">{D}_{{\text {it}}}{)} </tex-math></inline-formula> by the conductance method show that there is an ~51% reduction in the defect density after this posttreatment, a significant decrease. Finally, a TCAD simulation of different defect densities verifies the repair mechanism of deep-level defects.
In this study, the increment in the breakdown voltage of a SiC junction barrier Schottky (JBS) diode under negative bias stress (NBS) is investigated. However, when the SiC JBS exhibits an increase ...in breakdown voltage after NBS, its forward characteristic does not change. The variation in breakdown voltage increases under a higher stress voltage that is close to the breakdown voltage of SiC JBS without stress. Furthermore, the variation in breakdown voltage increases with a higher compliance current and at lower NBS temperature. The electric field of SiC JBS under NBS is simulated to clarify the variation in breakdown voltage under NBS. The electrical characteristics and the simulation of the electric field under NBS demonstrate that the increase in the breakdown voltage of SiC JBS after NBS is induced by the electron injection in the oxide layer of edge termination.
This study investigates the properties of a onetransistor- one-capacitor (1T1C) device that includes a transistor and ferroelectric random access memory (FeRAM) at the nanoscale. The hysteresis ...characteristics are presented. A simultaneous measurement of writing and reading was used. A difference was observed between the forward and reverse transconductance (gm) −V G curves, and the reason can be explained by the relationship between the operating voltage and coercive voltages. According to the relationship between gm and polarization, the polarization signal can be obtained using gm at the nano-scale. The remnant polarization of the 1T1C device per unit ferroelectric-layer area was confirmed by the polarization value of FeRAM via the Positive Up Negative Down method. Finally, the P-V loops obtained using gm values with different measurement ranges are also reported.
In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the ...HCD under different gate voltages (<inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {G}} </tex-math></inline-formula>) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {G}} </tex-math></inline-formula> increased, the HCD mechanism of the p- FinFET changed from electron-electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage (<inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {T}} </tex-math></inline-formula>) shift was observed for the n- FinFET. When <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {G}} </tex-math></inline-formula> increased to <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {T}}+1.2 </tex-math></inline-formula> V for the n- FinFET and to <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {T}} -{0.8} </tex-math></inline-formula> V for the p- FinFET, <inline-formula> <tex-math notation="LaTeX">\Delta \text{V}_{\text {T}} </tex-math></inline-formula> began to increase rapidly under hot carrier stress. The distributions of <inline-formula> <tex-math notation="LaTeX">\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{I}_{D} </tex-math></inline-formula> for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {G}} </tex-math></inline-formula> increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {G}} </tex-math></inline-formula> value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET.
In this study, the electrical performance and bending stress endurance of flexible low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) are enhanced by increasing the helium ...concentration (1500 sccm) during gate insulator (GI) manufacture to create a high-quality GI device. Experimental results confirm that the subthreshold swing (S.S.) and mobility of these new "high-flow" devices are better than those with a lower helium concentration, which we term "low-flow" devices. The flow of helium gas is increased to achieve a better-quality oxide layer. The energy-dispersive X-ray spectroscopy (EDS) line data show a clear enhancement in oxygen content in the devices under this helium gas process. After mechanical compression and tensile bending stresses of 100000 iterations in the channel width-axis direction, perpendicular to the channel, with bending at <inline-formula> <tex-math notation="LaTeX">{R} = {2} </tex-math></inline-formula> mm, the modified GI devices with their more Si-O bond content exhibit less stress damage in the GI layer than do low-flow devices. As a result, this new manufacturing condition can effectively reduce the electrical degradation after negative-bias temperature stress (NBTS), and improve the overall electrical performance.
This study focuses on the interaction between the oxide layer area of a transistor and its ferroelectric layer area. An experimental comparison of transistor oxide layer area demonstrates that the ...larger the ratio of oxide to ferroelectric layers, the larger the on/off ratio, thus improving performance. A subsequent experiment aimed to further demonstrate this in different sized devices, and changing the ratio of <inline-formula> <tex-math notation="LaTeX">\text{A}_{\text {HZO}}/\text{A}_{\text {SiO2}} </tex-math></inline-formula> (the area of HfZrO x divided by oxide layer) showed the same tendency as above, but also produced an unexpected finding in that a comparison of on/off ratio exhibits an abnormal electric characteristic. This study discusses this abnormal electric characteristic and proposes an explanatory physical model.
Fast recovery diodes (FRD) are widely used in transformer circuits for fast switching. Generally, in order to reduce forward voltage to achieve fast switching, the doping concentration is increased ...to reduce on-state resistance (R on ). This, however, will also increase reverse bias leakage as well as recovery time, resulting in a large amount of excess power consumption. In this letter, we use a unique low temperature supercritical fluid treatment process (LTSCF) to reduce this reverse bias leakage current, without affecting the on-state characteristics or switching characteristics. Experimental results show that the device's average reverse bias leakage was reduced by 65% after LTSCF.
The generation of defect states in p-MOSFETs under negative bias temperature instability (NBTI) has been extensively discussed in previous literature. However, only a few studies have discussed the ...relationship between interface defects and off -state leakage. Therefore, this article analyzes the impact of interface defects generated by NBTI on gate-induced drain leakage (GIDL). In general, GIDL is generated through band-to-band tunneling (BTBT) at large gate-to-drain bias (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {GD}} </tex-math></inline-formula>). In this article, NBTI causes an increase in GIDL at extremely low <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GD}} </tex-math></inline-formula>. By measuring at different temperatures and comparing the GIDL generated from hot carrier degradation (HCD), it was confirmed that the GIDL would still be generated through trap-assisted tunneling (TAT) and thermal excitation at an extremely low <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GD}} </tex-math></inline-formula>.
In this study, the threshold voltage (V T ) degradation mechanism for a hot electron stress (HES) under semi-ON state conditions in AlGaN/GaN high electron mobility transistors is analyzed. The drain ...current versus gate voltage (I D -V G ) characteristic curves indicate that V T shifts in the positive direction after the stress. However, an abnormal phenomenon that V T continuously shifts in the positive direction even after recovery is observed. A result comparison of a negative bias stress (NBS) experiment indicates that a hole recombination in pre-existing buffer defects is crucial. Therefore, a complete model of V T degradation mechanism is proposed. Moreover, the proposed model is confirmed through an illumination experiment and a Silvaco simulation.
This article investigates the influence of resistive protective oxide (RPO) layer density and hot carrier stress (HCS) degradation in n-channel lateral diffused silicon-on-insulator ...metal-oxide-semiconductor field-effect transistors. At the beginning of HCS at a higher gate voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula>), the threshold voltage shifts and subthreshold swing increase, but the ON-state current will still increase abnormally. The drain current and drain voltage (<inline-formula> <tex-math notation="LaTeX">{I}_{D} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{V}_{D} </tex-math></inline-formula>) transfer curves indicate that channel resistance or drift region resistance dominates degradation between low-<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula> and high-<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula> respectively. It also found different degradation behavior by extracting the resistances at low-<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula> and high-<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula> to stress time. In addition, technology computer-aided design (TCAD) software results show maximum impact ionization of high-<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula>, in which the direction of the electric field is toward RPO, resulting in the injection of holes into RPO during HCS. Finally, the simulated drain current and gate overdrive voltage curves for numerous interface states and numerous oxide traps show that the abnormal <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> enhancement is due to the hole trapping in the RPO and the degradation is closely related to the different density of RPO. In this article, we determine the mechanism of HCS degradation and propose methods to optimize high-voltage (HV) device performance and reliability.
