The Associative Memory (AM) system of the Fast TracKer (FTK) processor has been designed to perform pattern matching using as input the data from the silicon tracker in the ATLAS experiment. The AM ...is the primary component of the FTK system and is designed using ASIC technology (the AM chip) to execute pattern matching with a high degree of parallelism. The FTK system finds track candidates at low resolution that are seeds for a full resolution track fitting. The AM system implementation is named "Serial Link Processor" and is based on an extremely powerful network of 2 Gb/s serial links to sustain a huge traffic of data. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard which hosts four LAMB daughterboards. We also report on the performance of the prototypes (both hardware and firmware) produced and tested in the global FTK integration, an important milestone to be satisfied before the FTK production.
We have measured the W-boson mass M(W) using data corresponding to 2.2 fb(-1) of integrated luminosity collected in pp collisions at sqrts = 1.96 TeV with the CDF II detector at the Fermilab ...Tevatron collider. Samples consisting of 470,126 W → eν candidates and 624,708 W → μν candidates yield the measurement M(W) = 80,387 ± 12(stat.) ± 15(syst.) = 80,387 ± 19 MeV/c2. This is the most precise measurement of the W-boson mass to date and significantly exceeds the precision of all previous measurements combined.
The Silicon Vertex Trigger (SVT) is a processor developed at CDF experiment to perform online fast and precise track reconstruction. SVT is made of two pipelined processors, the Associative Memory, ...finding low precision tracks, and the Track Fitter, refining the track quality whith high precision fits. We will describe the architecture and the performances of a next generation track fitter, the GigaFitter, developed to reduce the degradation of the SVT efficiency due to the increasing instantaneous luminosity. The GigaFitter reduces the track parameter reconstruction to a few clock cycles and can perform many fits in parallel, thus allowing high resolution tracking at very high rate. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich in powerful DSP arrays. The FPGA is housed on a mezzanine board which receives the data from a subset of the tracking detector and transfers the fitted tracks to a Pulsar motherboard for the final corrections. Instead of the current 12 boards, one per sector of the detector, the final system will be much more compact, consisting of a single GigaFitter Pulsar board equipped with four mezzanine cards receiving the data from the entire tracking detector. Moreover, the GigaFitter modular structure is adequate to scale for much better performances and is general enough to be easily adapted to future High Energy Physics (HEP) experiments and applications outside HEP.
We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe ...the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.
We report a measurement of the bottom-strange meson mixing phase β(s) using the time evolution of B(s)(0)→J/ψ(→μ(+)μ(-))φ(→K(+)K(-)) decays in which the quark-flavor content of the bottom-strange ...meson is identified at production. This measurement uses the full data set of proton-antiproton collisions at √s=1.96 TeV collected by the Collider Detector experiment at the Fermilab Tevatron, corresponding to 9.6 fb(-1) of integrated luminosity. We report confidence regions in the two-dimensional space of β(s) and the B(s)(0) decay-width difference ΔΓ(s) and measure β(s)∈-π/2,-1.51∪-0.06,0.30∪1.26,π/2 at the 68% confidence level, in agreement with the standard model expectation. Assuming the standard model value of β(s), we also determine ΔΓ(s)=0.068±0.026(stat)±0.009(syst) ps(-1) and the mean B(s)(0) lifetime τ(s)=1.528±0.019(stat)±0.009(syst) ps, which are consistent and competitive with determinations by other experiments.
High performance embedded system for real-time pattern matching Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2017, Letnik:
845
Journal Article
Recenzirano
Odprti dostop
In this paper we present an innovative and high performance embedded system for real-time pattern matching. This system is based on the evolution of hardware and algorithms developed for the field of ...High Energy Physics and more specifically for the execution of extremely fast pattern matching for tracking of particles produced by proton–proton collisions in hadron collider experiments. A miniaturized version of this complex system is being developed for pattern matching in generic image processing applications. The system works as a contour identifier able to extract the salient features of an image. It is based on the principles of cognitive image processing, which means that it executes fast pattern matching and data reduction mimicking the operation of the human brain. The pattern matching can be executed by a custom designed Associative Memory chip. The reference patterns are chosen by a complex training algorithm implemented on an FPGA device. Post processing algorithms (e.g. pixel clustering) are also implemented on the FPGA. The pattern matching can be executed on a 2D or 3D space, on black and white or grayscale images, depending on the application and thus increasing exponentially the processing requirements of the system. We present the firmware implementation of the training and pattern matching algorithm, performance and results on a latest generation Xilinx Kintex Ultrascale FPGA device.
•A high performance embedded system for real-time pattern matching is proposed.•It is based on a system developed for High Energy Physics experiment triggers.•It mimics the operation of the human brain (cognitive image processing).•The process can be executed on 2D and 3D, black and white or grayscale images.•The implementation uses FPGAs and custom designed associative memory (AM) chips.
We combine searches by the CDF and D0 Collaborations for a Higgs boson decaying to W+W-. The data correspond to an integrated total luminosity of 4.8 (CDF) and 5.4 (D0) fb(-1) of pp collisions at ...square root(s) = 1.96 TeV at the Fermilab Tevatron collider. No excess is observed above background expectation, and resulting limits on Higgs boson production exclude a standard model Higgs boson in the mass range 162-166 GeV at the 95% C.L.
The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of ...pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130 nm CMOS technology. The pixel dimension is 50 by 50 mum 2 . The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm 2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.
Thin pixel development for the SuperB silicon vertex tracker Rizzo, G.; Avanzini, C.; Batignani, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
09/2011, Letnik:
650, Številka:
1
Journal Article
Recenzirano
The high luminosity SuperB asymmetric
e
+
e
−
collider, to be built near the INFN National Frascati Laboratory in Italy, has been designed to deliver a luminosity greater than 10
36
cm
−2
s
−1 with ...moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5
cm), resolution of
10
–
15
μ
m
in both coordinates, low material budget (
<
1
%
X0), and able to withstand a background rate of several tens of MHz/cm
2. The ambitious goal of designing a thin pixel device with these stringent requirements is being pursued with specific R&D programs on different technologies: hybrid pixels, CMOS MAPS and pixel sensors developed with vertical integration technology. The latest results on the various pixel options for the SuperB SVT will be presented.
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