In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis ...shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.
A new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between ...inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1/f noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1/f noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1/f noise spectra of switched MOSFET's, which is useful for 1/f noise model validation and analog circuit design.
A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid ...gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.
An integrated spectrum analyzer is useful for built-in self-test purposes, software-defined radios, or dynamic spectrum access in cognitive radio. The analog/RF performance is impaired by a number of ...factors, including thermal noise, phase noise, and nonlinearity. In this paper, we present an integrated circuit with two integrated RF-frontends, of which the outputs are crosscorrelated in digital baseband. We show by theory and measurements that the above-mentioned impairments are mitigated by this technique. The presented 65-nm CMOS prototype operates at 1.2 V, and obtains a noise floor below -169 dBm/Hz, an IIP 3 of +25 dBm, and more than 20 dB of phase-noise reduction. In a special high-impedance mode, an even lower noise floor below -172 dBm/Hz is obtained.
Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in ...electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.
A 1-4-GHz 4-element phased array receiver front-end demonstrates spatial interferer rejection using null steering. Element phase and amplitude control are performed by a switched-capacitor vector ...modulator with integrated downconversion, utilizing a rational sine/cosine approximation. The 65-nm CMOS receiver achieves more than 20 dB of spatial interferer rejection up to an angular separation of 15°.
Spectrum sensing is one of the key characteristics of a cognitive radio. Energy detection provides maximum flexibility by not relying on any prior knowledge, but suffers from an SNR-wall due to noise ...uncertainty. Crosscorrelation of the outputs of two receiver paths is a technique to reduce the noise level of the total receiver, and hence improves the SNR. The reduction of the noise is limited by correlated noise originating from shared components near the antenna. In this paper we explore the use of a separate antenna for each receiver for crosscorrelation spectrum sensing. One immediate advantage is that due to the removal of the splitter, which was necessary to interface the single antenna to two receivers, the SNR improves, significantly reducing the required measurement time. A lot of the noise correlation can be removed, leading to a lower residual noise floor. The noise at each antenna will still be partially correlated due to mutual coupling, spatial noise correlation and man-made noise. We show that some signal power can be lost in the sensing process due to partial decorrelation of the signal at the two antennas. Fortunately, this seems to be a problem only in highly mobile environments, which makes the use of two-antenna crosscorrelation spectrum sensing an interesting solution towards more reliable energy detection.
Distortion cancellation by polyphase multipath circuits Mensink, E.; Klumperink, E.A.M.; Nauta, B.
IEEE transactions on circuits and systems. I, Fundamental theory and applications,
09/2005, Letnik:
52, Številka:
9
Journal Article
Recenzirano
Odprti dostop
It is well known that in balanced (or differential) circuits, all even harmonics are canceled. This cancellation is achieved by using two paths and exploiting phase differences of 180/spl deg/ ...between the paths. The question addressed in this paper is: what distortion products (harmonics and intermodulation products) are canceled if more than two paths (and phases) are used? These circuits are called polyphase multipath circuits. It turns out that the more paths (and phases) are used, the more distortion products are canceled. Unfortunately, some intermodulation products cannot be canceled without also canceling the desired signal. An analysis of the impact of mismatch between the paths shows that the suppression of distortion products will be larger if more paths are used. As an application example, the design of an upconversion mixer with a clean output spectrum is presented.
A spectrum analyzer requires a high linearity to handle strong signals, and at the same time a low NF to enable detection of much weaker signals. This is not only important for lab equipment, but ...also for the spectrum sensing part of cognitive radio, where low cost and integration is at a premium. Often there is a trade-off between linearity and noise: improving one degrades the other. Crosscorrelation can break this trade-off by reducing noise at the expense of measurement time. An existing RF frontend in CMOS-technology with IIP3 = +11 dBm and NF = 5.5 dB is duplicated and attenuators are put in front to increase linearity to IIP3 = +24 dBm. The attenuation degrades NF, but by using crosscorrelation of the outputs of the two frontends, the effective NF is reduced to around 5 dB. In total, this results in a spurious-free dynamic range of 88 dB in 1 MHz resolution bandwidth.
Noise cancelling in wideband CMOS LNAs Bruccoleri, F; Klumperink, E A M; Nauta, B
Digest of technical papers - IEEE International Solid-State Circuits Conference,
01/2002
Journal Article
Techniques of noise cancellation in wideband CMOS low noise amplifiers (LNA) were presented. Elementary wideband amplifiers showed a severe trade-off between their frequencies and the matching ...requirement Z sub(IN)=R sub(S), failing to achieve sub-3dB noise figure (NF). The LNA for 2dB wideband NF used 0.25 mu m CMOS, while driving the output bond pad capacitance C sub(LOAD )=0.2 pF load.
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