A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band ...nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock ...define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P 1dB =2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).
The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology Blaakmeer, S.C.; Klumperink, E.; Leenaerts, D.M.W. ...
IEEE journal of solid-state circuits,
12/2008, Letnik:
43, Številka:
12
Journal Article, Conference Proceeding
Recenzirano
Odprti dostop
This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the ...voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm 2 in 65 nm CMOS.
N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path ...notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50-Ω environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4-2.8 dB. The rejection at the notch frequency is 21-24 dB, P 1 dB > +2 dBm, and IIP3 > +17 dBm.
Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably ...high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but ...the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-/spl mu/m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 /spl mu/m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.
Current analog harmonic rejection mixers typically provide 30-40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that ...uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30-45 dB.
In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out- of-band interference (OBI). Besides ...harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA amplifies signal and interference with equal gain. Even a low gain of 6dB can clip OdBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used, but are sensitive to phase and gain mismatch. Indeed the HR in shows a large spread, whereas other work only shows results from one chip. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch.
In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same ...frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.
Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative ...feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.
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