This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the ...oscillator's close-in phase noise. More specifically, it is shown that the 1/f/sup 3/ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f/sup 3/ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching.
In this paper, we present measurements and simulation of random telegraph signal (RTS) noise in n-channel MOSFETs under periodic large signal gate-source excitation (switched bias conditions). This ...is particularly relevant to analog CMOS circuit design where large signal swings occur and where LF noise is often a limiting factor in the performance of the circuit. Measurements show that, compared to steady-state bias conditions, RTS noise can decrease but also increase when the device is subjected to switched bias conditions. We show that the simple model of a stationary noise generating process whose output is modulated by the bias voltage is not sufficient to explain the switched bias measurement results. Rather, we propose a model based on cyclostationary RTS noise generation. Using our model, we can correctly model a variety of different types of LF noise behavior that different MOSFETs exhibit under switched bias conditions. We show that the measurement results can be explained using realistic values for the bias dependency of /spl tau//sub c/ and /spl tau//sub e/.
In this paper, an in-depth analysis of switched-resistor (S-R) techniques for implementing low-voltage low-distortion tunable active- RC filters is presented. The S-R techniques make use of ...switch(es) with duty-cycle-controlled clock(s) to achieve tunability of the effective resistance and, hence, the RC time constant. The characteristics of two S-R networks utilizing one set (S-1R) and two sets (S-2R) of switch and resistor combinations are analyzed. It will be shown that the S-2R network outperforms the S-1R counterpart in terms of finite-slew-rate-induced distortion, frequency translation, and noise performance. In order to extend the tuning range, an S-R bank scheme is also described. The theoretical analysis was verified by an experiment on a 100-kHz first-order S-R filter prototype, implemented using discrete elements, where several advantages of the S-2R over the S-1R networks are demonstrated. Simulations of 10-MHz low-pass filters based on the S-1R and S-2R techniques in a standard 0.18- mum CMOS process are also included for performance comparison in practical on-chip filter implementations.
Spurious-Free Dynamic Range of a Uniform Quantizer Oude Alink, M.S.; Kokkeler, A.B.J.; Klumperink, E. ...
IEEE transactions on circuits and systems. II, Express briefs,
06/2009, Letnik:
56, Številka:
6
Journal Article
Recenzirano
Odprti dostop
Quantization plays an important role in many systems where analog-to-digital conversion and/or digital-to-analog conversion take place. If the quantization error is correlated with the input signal, ...then the spectrum of the quantization error will contain spurious peaks. Although analytical formulas describing this effect exist, numerical evaluation can take much effort. This brief provides approximations for the spurious-free dynamic range (SFDR) of a uniform quantizer with a single sinusoidal input, with and without additive Gaussian noise. It is shown that the SFDR increases by approximately 8 dB/bit, in case there is no noise. Generalizing this result to multitone inputs results in an additional 2 dB/bit per additional tone. Additive Gaussian noise decorrelates the sinusoid(s) and the quantization error, which results in a dramatic increase in SFDR.
An inductorless LNA with active balun is designed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common gate stage and a common source stage with ...replica biasing to maximize balanced operation. The NF is designed to be around 3 dB by using the noise canceling technique. Its best performance is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees, 15 dB gain, S11<-14 dB, IIP3=0 dBm and IIP2 higher than +20 dBm at a total power consumption of 21 mW. The circuit is fabricated in a baseline 65 nm CMOS process, with an active area of only 0.01 mm 2 . The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output.
This paper describes a combination of a Weaver mixer and an N-path filter for a superheterodyne receiver with a reconfigurable frequency plan. It uses an N-path topology driven with two different ...frequencies, effectively realizing a frequency shift together with band-pass filtering. To reduce transfers via harmonics other than the fundamental, a harmonic rejection scheme is used. A 28nm FDSOI CMOS implementation with 30 dB harmonic rejection and an out-of-band IIP3 of >20dBm is demonstrated.
All-pass filter circuits can implement a time delay but, in practice, show delay and gain variations versus frequency, limiting their useful frequency range. This brief derives analytical equations ...to estimate this frequency range, given a certain maximum allowable budget for variation in delay and gain. We analyze and compare two well-known gm - RC first-order all-pass circuits, which can be compactly realized in CMOS technology and relate their delay variation to the main pole frequency. Modeling parasitic poles and putting a constraint on gain variation, equations for the maximum achievable pole frequency and delay variation versus frequency are derived. These equations are compared with simulation and used to design and compare delay cells satisfying given design goals.
This paper describes three RF self-interference reduction techniques for full-duplex wireless links, which specifically target integration in compact radios. Concretely, a self-interference ...cancelling front-end, a dual-polarized antenna, and an electrical balance duplexer are proposed. Each technique offers specific benefits in terms of implementation density, self-interference rejection, bandwidth and flexibility. Depending on their characteristics, they can be adopted in different next-generation full-duplex applications and standards. All concepts are prototyped, and achieve at least 45dB of self-interference reduction over more than 10MHz bandwidth.
A new measurement setup is presented that allows the observation of 1/f noise spectra in MOSFET's under switched bias conditions in a wide frequency band (10 Hz-100 kHz). When switching between ...inversion and accumulation, MOSFET's of different manufacturers invariably show reduced 1/f noise power density for frequencies below the switching frequency. At low frequencies (10 Hz), a 5-8 dB reduction in intrinsic 1/f noise power density is found for different devices, largely independent of the switching frequency (up to 1 MHz). The switched bias measurements render detailed wideband 1/f noise spectra of switched MOSFET's, which is useful for 1/f noise model validation and analog circuit design.
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