A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology. The PA is constructed as a cascode stage formed by a standard thin-oxide device and a ...dedicated novel high voltage extended-drain thick-oxide device. Both devices are implemented without using additional masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (P out ) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off. Stress tests indicate the reliability of both the novel high voltage device and the design.
A Fully Integrated Ka-Band VSAT Down-Converter de Jong, G. W.; Leenaerts, D. M. W.; van der Heijden, E.
IEEE journal of solid-state circuits,
07/2013, Letnik:
48, Številka:
7
Journal Article, Conference Proceeding
Recenzirano
A fully integrated Ka-band down-converter for VSAT applications will be demonstrated. The high-band (21.4-22.0 GHz) and the low-band (19.2-20.2 GHz) are simultaneously down converted to the L-band ...(950-2150 MHz) and independently accessible by two users. The SSB-NF is better than 8 dB at a conversion gain of 25 dB (20 dB) for the low-band (high-band). The integrated PLL achieves a state-of-the-art integrated phase noise of 1.2° rms. The total solution consumes 548 mW.
The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it ...suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3sigma) over the temperature range from -22degC to 85degC . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm 2 and draws 34 muA from a 1.2 V supply at room temperature.
A temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55°C to 125°C , the frequency spread of the ...complete reference is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm 2 and draws 42.6 μA from a 1.2-V supply at room temperature.
A 1.95 GHz Sub-1 dB NF, +40 dBm OIP3 WCDMA LNA Module Bergervoet, J.; Leenaerts, D. M. W.; de Jong, G. W. ...
IEEE journal of solid-state circuits,
07/2012, Letnik:
47, Številka:
7
Journal Article, Conference Proceeding
Recenzirano
A silicon integrated LNA for WCDMA cellular infrastructure applications, e.g., base stations will be demonstrated. The LNA is designed for WCDMA band II, i.e., 1.92-1.98 GHz, and reaches a 0.9 dB NF ...at 27 ° C and 1.2 dB at 65 ° C. A 0.1 dB NF improvement is obtained when the first gain stage is implemented using a cascode topology rather than a two-stage topology. The output IP3 is +40 dBm (+38 dBm) at 27 ° C and +37 dBm (+36 dBm) at 65 ° C for the two-stage (cascode) topology. Both options have an input return loss better than 20 dB and output return loss better than 20 dB. A bypass mode and variable attenuation are provided to cope with large input signals. Implemented in a SiGe:C BiCMOS technology, the two-die MMIC is packaged on a single laminate. The total solution consumes just below 200 mA from a 5 V supply.
A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, ...consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 /spl mu/m BiCMOS technology and draws 78mA from a 2.5-V supply.
Impulse-Based Scheme for Crystal-Less ULP Radios Drago, S.; Sebastiano, F.; Breems, L.J. ...
IEEE transactions on circuits and systems. I, Regular papers,
05/2009, Letnik:
56, Številka:
5
Journal Article
Recenzirano
Odprti dostop
This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), ...with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ¿W with a clock generator inaccuracy of only 1%.
This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-μm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the ...locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <;-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <;-73dBc across the whole locking range.
A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer van de Beek, R.C.H.; Leenaerts, D.M.W.; van der Weide, G.
IEEE journal of solid-state circuits,
07/2006, Letnik:
41, Številka:
7
Journal Article, Conference Proceeding
Recenzirano
This paper describes a 3-band (mode 1) multi-band-OFDM UWB synthesizer implemented in a 0.25-mum SiGe BiCMOS process. The interference-robust, fast-hopping synthesizer uses one single-sideband (SSB) ...mixer for frequency shifting. A single phase-locked loop (PLL) generates the steady input signals for the SSB-mixer. Crucial in the design is a divide-by-5 frequency divider that generates quadrature signals at a frequency of 528 MHz. The 0.44 mm 2 fully integrated synthesizer consumes 52 mW from a 2.7 V supply. Out-of-band spurious tones are below -50 dBc, allowing co-operability with WLAN applications in the 2.4 GHz and 5 GHz range. The integrated phase noise is below 2deg rms. The measured frequency transition time is well below the required 9.5 ns
In this brief we present two architectures for digital division by odd numbers suitable for implementation in high-speed prescalers. First, we show a technique that delivers accurate in-phase and ...quadrature outputs over a wide frequency range from an inherently symmetrical circuit structure, which is particularly suited to the realization of image-rejection transceiver architectures with offset local oscillator frequency. The second technique focuses on generating precise 50% duty cycle outputs, which are intended for direct mixer drive to achieve low output dc offset and second-order input intercept point. Both concepts can be realized in a wide range of logic forms. Demonstrator circuits implemented in high-speed current-mode logic have been fabricated in 0.18-m digital CMOS technology, and both techniques show robust odd-number division. The test chips consume approximately 7 mA each from a 1.8-V supply.
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