Densely aligned sub-10 nm graphene nanoribbons are desirable for scale-up applications in nanoelectronics. We implemented directed self-assembly of block-copolymers in combination with nanoimprint ...lithography to pattern sub-10 nm half-pitch nanoribbons over large areas. These graphene nanoribbons have the highest density and uniformity to date. Multichannel field-effect transistors were made from such nanoribbons, and the transport characteristics of transistors were studied. Our work indicates that a large ribbon-to-ribbon width variation in a multichannel FET can lead to nonsynchronized switching characters of multiple graphene channels and thus a poor ON/OFF current ratio. Through process optimization, we have created 8 nm half-pitch graphene nanoribbons with the minimal ribbon-to-ribbon width variation of ∼2.4 nm (3σ value). The corresponding transistors exhibit an ON/OFF current ratio >10, which is among the highest values ever reported for transistors consisting of densely arranged graphene nanoribbons. This work provides important insights for optimizing the uniformity and transport properties of lithographically patterned graphene nanostructures. In addition, the presented fabrication route could be further developed for the scalable nanomanufacturing of graphene-based nanoelectronic devices over large areas.
New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve ...as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.
We fabricated hexagonal graphene nanomeshes (GNMs) with sub-10 nm ribbon width. The fabrication combines nanoimprint lithography, block-copolymer self-assembly for high-resolution nanoimprint ...template patterning, and electrostatic printing of graphene. Graphene field-effect transistors (GFETs) made from GNMs exhibit very different electronic characteristics in comparison with unpatterned GFETs even at room temperature. We observed multiplateaus in the drain current−gate voltage dependence as well as an enhancement of ON/OFF current ratio with reduction of the average ribbon width of GNMs. These effects are attributed to the formation of electronic subbands and a bandgap in GNMs. Such mesoscopic graphene structures and the nanofabrication methods could be employed to construct future electronic devices based on graphene superlattices.
We demonstrate a method that uses the pillars on a stamp to cut and exfoliate graphene islands from a graphite and then uses transfer printing to place the islands from the stamp into the device ...active-areas on a substrate with a placement accuracy potentially in nanometers. The process can be repeated to cover all device active-areas over an entire wafer. We also report the transistors fabricated from the printed graphene. The transistors show a hole and electron mobility of 3735 and 795 cm2/V-s, respectively, and a maximum drive-current of 1.7 mA/μm (at V DS = 1 V), which are among the highest reported for room temperature. The effects of various transferring and fixing layers on sticking graphenes to a stamp and to a substrate, respectively, were also investigated.
We report fabrication and characterization of a novel real-time, label-free DNA detector, that uses a long nanofluidic channel to stretch a DNA strand and a nanogap detector (with a gap as small as 9 ...nm) inside the channel to measure the electrical conduction perpendicular to the DNA backbone as it moves through the gap. We have observed electrical signals caused by 1.1 kilobase-pair (kbp) double-stranded (ds)-DNA passing through the gap in the nanogap detectors with a gap equal to or less than 13 nm.
To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified ...charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe2 flakes, whereas they cannot be generated in widely studied few-layer MoS2 transistors. Such charge-trapping characteristics of WSe2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.
