Polar modulated RF amplifiers have the potential to enhance efficiency while achieving sufficient linearity for a signal having non-constant envelope. However, switching modulators used in such ...architectures to generate the envelope signal are difficult to implement because of the high bandwidth and low switching ripple requirement, while achieving high efficiency even at large power back-off. This paper presents a wideband supply modulator for a 20 MHz RF bandwidth polar modulated PA. Realized in 65 nm CMOS, it consists of a cascoded nested Miller compensated linear amplifier and a class D switching amplifier. The class-AB linear amplifier with cascoded Miller compensation in the modulator reduces the output switching ripple to 4.3 mVrms at a switching frequency of 118 MHz. With an optimized design the modulator achieves a maximum efficiency of 87.5% and a small signal -3 dB bandwidth of 285 MHz. At 10 dB back-off the efficiency is more than 40%. The modulator can deliver 22.7 dBm output power to a 5.3 Omega load. It satisfies the linearity requirement of IEEE 802.11g WLAN signal when tested in a real polar modulated amplifier.
Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably ...high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it ...suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3sigma) over the temperature range from -22degC to 85degC . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm 2 and draws 34 muA from a 1.2 V supply at room temperature.
This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ ...was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.
CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is ...described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3- mu m CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described.< >
Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in ...electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.
A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid ...gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.
In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same ...frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.
In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the ...limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applied.
Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. ...This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a software-defined radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 V pp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers
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