In this paper, we compare a shift register (SR) to a delay-locked loop (DLL) for flexible multiphase clock generation, and motivate why a SR is not only more flexible but often also better. For a ...given power budget, we show that a SR almost always generates less jitter than a DLL, assuming both are realized with current-mode logic. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For -phase clock generation, a SR also functions as a divide-by- and requires a voltage-controlled oscillator with times higher frequency. However, this does not necessary lead to more power consumption and can even have advantages like higher Q and less area for the inductors.
Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but ...the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-/spl mu/m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 /spl mu/m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.
Impulse-Based Scheme for Crystal-Less ULP Radios Drago, S.; Sebastiano, F.; Breems, L.J. ...
IEEE transactions on circuits and systems. I, Regular papers,
05/2009, Letnik:
56, Številka:
5
Journal Article
Recenzirano
Odprti dostop
This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), ...with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ¿W with a clock generator inaccuracy of only 1%.
It is well known that in balanced (or differential) circuits, all even harmonics are canceled. This cancellation is achieved by using two paths and exploiting phase differences of 180/spl deg/ ...between the paths. The question addressed in this paper is: what distortion products (harmonics and intermodulation products) are canceled if more than two paths (and phases) are used? These circuits are called polyphase multipath circuits. It turns out that the more paths (and phases) are used, the more distortion products are canceled. Unfortunately, some intermodulation products cannot be canceled without also canceling the desired signal. An analysis of the impact of mismatch between the paths shows that the suppression of distortion products will be larger if more paths are used. As an application example, the design of an upconversion mixer with a clean output spectrum is presented.
This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in ...a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- mu hbox m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 , times , 0.45 hbox mm 2 . With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be - 126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.
In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out- of-band interference (OBI). Besides ...harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA amplifies signal and interference with equal gain. Even a low gain of 6dB can clip OdBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used, but are sensitive to phase and gain mismatch. Indeed the HR in shows a large spread, whereas other work only shows results from one chip. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch.
The operating environment of mobile phones fluctuates continuously, due to changing handling conditions and nearby objects. The resulting fluctuations in antenna impedance cause both a decrease in ...link quality and a higher standing wave ratio, that requires more robust and hence less efficient power amplifier implementations. In this paper, an automatic antenna tuner system for handheld applications is presented that uses two series reactances combined with three simple RF peak detectors to sense both reactive and real impedance mismatches. The control loop only requires low-frequency electronics which makes it low cost, low power and relatively easy to integrate. Measurements on a demonstrator system show correct behaviour for voltage standing-wave ratio up to 10.
This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new ...circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-/spl mu/m CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V.
The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, ...the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.
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