In this paper, an in-depth analysis of switched-resistor (S-R) techniques for implementing low-voltage low-distortion tunable active- RC filters is presented. The S-R techniques make use of ...switch(es) with duty-cycle-controlled clock(s) to achieve tunability of the effective resistance and, hence, the RC time constant. The characteristics of two S-R networks utilizing one set (S-1R) and two sets (S-2R) of switch and resistor combinations are analyzed. It will be shown that the S-2R network outperforms the S-1R counterpart in terms of finite-slew-rate-induced distortion, frequency translation, and noise performance. In order to extend the tuning range, an S-R bank scheme is also described. The theoretical analysis was verified by an experiment on a 100-kHz first-order S-R filter prototype, implemented using discrete elements, where several advantages of the S-2R over the S-1R networks are demonstrated. Simulations of 10-MHz low-pass filters based on the S-1R and S-2R techniques in a standard 0.18- mum CMOS process are also included for performance comparison in practical on-chip filter implementations.
A modeling approach is presented that calculates an accurate open-loop transfer characteristic for a boost converter that employ peak current-mode control (PCMC). Many techniques exist for modeling a ...PCMC-based boost converter; however, all these techniques focus on purely resistive loads and are not always accurate for a purely capacitive load. In this paper, a new modeling technique is presented, which is simple and gives accurate results for both capacitive and resistive loads. Furthermore, the useful expressions for dc gain and pole locations of a boost converter operating in continuous-conduction mode with PCMC are derived and compare well to simulations and measurements.
An 8-10 GHz X-band upconversion quadrature mixer stage implemented in 250 nm SiGe BiCMOS is presented. Orthogonality of the spurious responses caused by clock feed through, I/Q mismatch and baseband ...harmonics after self-mixing was exploited to realize a baseband calibration scheme reducing all in-band spurs down to below -73dBc, for baseband signals up to a bandwidth of 2MHz and with an IF center frequency up to 100MHz. Utilizing a low-frequency output spectrum analysis of an integrated self-mixer at the upconversion mixer output for calibration, eliminates the need for expensive microwave frequency spectrum analyzers.
In this paper, we present measurements and simulation of random telegraph signal (RTS) noise in n-channel MOSFETs under periodic large signal gate-source excitation (switched bias conditions). This ...is particularly relevant to analog CMOS circuit design where large signal swings occur and where LF noise is often a limiting factor in the performance of the circuit. Measurements show that, compared to steady-state bias conditions, RTS noise can decrease but also increase when the device is subjected to switched bias conditions. We show that the simple model of a stationary noise generating process whose output is modulated by the bias voltage is not sufficient to explain the switched bias measurement results. Rather, we propose a model based on cyclostationary RTS noise generation. Using our model, we can correctly model a variety of different types of LF noise behavior that different MOSFETs exhibit under switched bias conditions. We show that the measurement results can be explained using realistic values for the bias dependency of /spl tau//sub c/ and /spl tau//sub e/.
Spurious-Free Dynamic Range of a Uniform Quantizer Oude Alink, M.S.; Kokkeler, A.B.J.; Klumperink, E. ...
IEEE transactions on circuits and systems. II, Express briefs,
06/2009, Letnik:
56, Številka:
6
Journal Article
Recenzirano
Odprti dostop
Quantization plays an important role in many systems where analog-to-digital conversion and/or digital-to-analog conversion take place. If the quantization error is correlated with the input signal, ...then the spectrum of the quantization error will contain spurious peaks. Although analytical formulas describing this effect exist, numerical evaluation can take much effort. This brief provides approximations for the spurious-free dynamic range (SFDR) of a uniform quantizer with a single sinusoidal input, with and without additive Gaussian noise. It is shown that the SFDR increases by approximately 8 dB/bit, in case there is no noise. Generalizing this result to multitone inputs results in an additional 2 dB/bit per additional tone. Additive Gaussian noise decorrelates the sinusoid(s) and the quantization error, which results in a dramatic increase in SFDR.
Current analog harmonic rejection mixers typically provide 30-40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that ...uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30-45 dB.
This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the ...oscillator's close-in phase noise. More specifically, it is shown that the 1/f/sup 3/ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f/sup 3/ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching.
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The ...VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3ps rms .
In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF ...capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used.
A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 /spl mu/m CMOS process. The regulator is able to deliver peak current ...transients of 300 mA, while the output voltage remains within a margin of 10% around the nominal value. The circuit draw's a static quiescent current of 750 /spl mu/A during normal operation, and includes a power-down mode with only 10 /spl mu/A current consumption. The die area is 1 mm/sup 2/, and can be scaled proportional to the maximum peak current. Special precautions have been taken to allow 5 V in the 3.3 V process.
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