A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in ...CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm/sup 2/ in 0.8 /spl mu/m CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.
A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate ...with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.
Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential ...interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk
This work presents a fully integrated multi-band frequency synthesizer that is capable of creating wide-band linear frequency sweeps of very short duration. The main aim is to create a flexible ...waveform generation system, requiring distribution of a low frequency reference rather than RF signals. By using a phase-locked loop, frequency multiplication (rather than shifting) occurs. This allows for a narrow band and low frequency reference signal, allowing digital reference generation and thus providing a large degree of flexibility. Chirps with a bandwidth of 1 GHz (in X-band) and duration as short as 10 μs can be created. The chip can be operated in either pulsed or CW mode. The small external size of the package, which measures 5×5 mm 2 means that local RF generation is possible even in X-band arrays with small antenna element pitch.
Co-existence problems in a mobile terminal environment pose strict requirements on the linearity of a front-end receiver. In this paper, active feedback is explored as a means to relax such ...requirements by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture addresses some of the most common problems of integrated RF filters, while maintaining their inherent tunability. Through a simplified and intuitive analysis, the operation of the receiver is examined and the design parameters affecting the filter characteristics, such as bandwidth and stopband rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-off between noise, linearity and harmonic radiation. A prototype designed in a standard 65 nm CMOS process occupies <;0.06 mm 2 and utilizes an RF channel-select filter with a 1 to 2.5 GHz tunable center frequency to achieve 48 dB of stopband rejection and a wideband IIP3 >; +12 dBm.
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat ...transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
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