This article described the Advanced Encryption Standard (AES) encryption and decryption process without using lookup tables in the MixColumns transformation and parallelizing the transformation ...process implemented in the Field Programmable Gate Array (FPGA) hardware. Parallelism of the hardware process conducted to the transformation of key schedule, addroundkey, subbyte and shiftrows (subshift) and mixcolumns in the first 5 rounds of the encryption process. The decryption process was parallelized in subshift transformations, both transformations were implemented at the same time. This research produced a modified AES encryption and decryption method and algorithm with the aim of minimizing the resources required for hardware implementation. The method in this article was applied to Xilinx ISE 14.7 software. The experimental results showed that the encryption process required 2,357 slice LUT's, 845 occupied slices and 26 IOB's, while the decryption process required 2,896 LUT's, 1,323 occupied slices and 26 IOB's resources. The encryption and decryption processes each took an average of 2.891 nanoseconds and 3.467 nanoseconds for every 128 bits of data. This approach leads us to obtain a component with minimum resources and enough computational speed.
Statistical formula processing an image data is commonly used in image processing. In software processing this formula and accessing data stored in memory is an easy task, but in hardware ...implementation, it is more difficult task due to many of constraints. This article presents hardware implementation of mean ＆ variance statistic formula in effective and efficient way using FGPA Device. The design of circuit for both formulas proposed in this article need only two additions component (in two accumulators) and two shift-right-registers will be used for divisor circuits, one subtractor and one multiplier. In the experiment, processing an image size 8x8 pixels need 64 clocks cycle to conclude the mean ＆ variance calculations. More than 1024 additions component is needed in some design so this design is more efficient.
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk ...mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i. Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i AbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i. Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
Line encoding is crucial especially in data communication which part of internet of things environment. Line encoding doing encode raw bit stream and applying some rules before transmitting to ...transmission medium. Some example of encoding technique is: non-return zero encoding (NRZ), return-zero encoding, and Manchester encoding. Manchester coding technique have advantages compared to NRZ and RZ coding. Manchester coding can recognize bit interval and will have no problem to encode long same bit stream. Manchester encoder commonly built using logical XOR gate, with clock and bit stream as input and output of XOR gate will determined as encoded signal. The common design has a weakness since the clock is use in operation, and the output will be separate into two parallel bit stream. Common design also has spike glitch in some transitions. In this work, the new design of Manchester encoder using FPGA device is proposed to overcome common design problems and suitable to be implemented in IoT environment.
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk ...mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
This study explains the comparison of techniques for cropping existing in Matlab for graylevel images on periapical radiographs of human teeth. Some cropping techniques in Matlab are rectangular ...crop, square crop, circular crop, ellipse crop, polygon crop. This research will explain how each existing cropping technique will give different results based on their respective shapes. So that eventually will produce the most appropriate cropping techniques among several existing cropping techniques in mathlab. The five cropping techniques that have been mentioned here where the four existing cropping techniques namely rectangular crop, square crop, circular crop, ellipse crop still carry other objects that are not needed in research, so it is not appropriate to be used for research objects that have irregular shapes. Appropriate cropping technique is polygon cropping because it is able to identify research objects that have irregular shapes.
This paper presents an analysis of the modeling of reactive power compensation using renewable energy from sunlight through photovoltaic to eliminate harmonic signals in the electricity network with ...a three-phase active power system filter. Electric energy supply comes from three-phase electricity sources in the form of a sinusoid. Non-linear loads such as electronic devices and electrical equipment connected to the grid generate harmonics signals; can make the format of electrical energy distorted. This nonlinear load draws electric current in the form of non-sinusoid. This format increases Total Harmonic Distortion (THD), thereby worsening the performance of electrical equipment. An active power filter is a very effective method in reducing harmonics signals and increasing the quality performance of electricity. This power filter works by injecting compensation current into the grid. The energy that is injected comes from the direct current output voltage (DC) of the photovoltaic link stored in the capacitor via a Voltage Source Inverter (VSI) switch. The compensation current has the same format as the harmonics current but differs in 180°. The main parts of this power filter include the Reference Signal Generating Unit, PI Controller, VSI Switch Signal Ignition Gate Generator, Energy Storage Circuit (Battery), and Photovoltaic. Simulation modeling using Matlab Simulink Tools to reduce THD levels by IEEE 519 standards. Simulation results show a significant decrease in Total Harmonic Distortion (THD), where the grid before compensation contains THD of 29.74% and after injection of 2.25%. So this modeling is worth proposing as an active filter in a power system.
Research on plantation products has now turned to non-destructive research, this is because the quality of plantation products still uses the manual method of relying on sight or hand size to ...distinguish which is good, damaged, ripe, raw, large or small. Of course, the results are inconsistent, due to differences in perceptions of sight and the size of the hand between farmers with each other. Now the researcher conduct research based on the analysis of image processing. Where color extraction features (other than shape and texture) which is the stage of extracting the information contained in an object in a digital image. This information is used to distinguish between one object and another object at the stage of grouping/identification analysis based on color. In this case, the author extracts color features based on the minimum and maximum values for each component of the values R, G, B, H, S, V, H, C and L using the RGB, HSV and HCL methods. Thus, it can be seen the differences in the results of color extraction that characterize the object: Medan oranges of the three methods. The conclusion resulted from this research can't be used as a basis for determining specific the characteristics of each oranges class, because there is any overlap minimum-maximum value.
Fingerprint identification systems are vulnerable to attempted authentication fraud by creating fake fingerprints that mimic the live. This paper proposes method to detect whether a fingerprint is ...live fingerprint or fake fingerprint using Convolutional Neural Network (CNN). We construct a features database of distances among minutiaes of fingerprints, where the distance calculation is based-on Euclidean Distance. Furthermore, the distance features database that has been constructed is classified using the CNN. CNN is a deep learning method designed for machine learning processes so that computers recognize objects in an image and this method has capability classifying an object. The numerical results have shown that the best accuracy achieves 99.38% when the learning rate is 0.001 with the epoch of 100.
Digital images are images in digital formats or digital media such as hard drives. Digital images consist of bits (0 or 1) called pixels and have a high capacity for storing data and information. ...Steganography techniques try to hide the existence of confidential data. The Steganography technique perfectly closes secret messages in carrier images with high level security. Information and data will be manipulated so that it can be detected by human eyes. Least Significant Bit (LSB) is the method used in this study. The embedding and extracting processes in the proposed algorithms are performed using Matlab software and FPGA-based hardware simulation using Xilinx ISE. The purpose of this study is to compare the process speed of the LSB steganography algorithm in the two implementations. The input data on the encryption used is data in binary form and Red Green Blue (RGB) images and output data in stego images. Meanwhile, the input data in the decryption is a stego image and the output data is in the form of binary data. The experimental results showed that the steganography algorithm had been successfully performed on FPGA and Matlab. However, the process on FPGA is faster than the process on Matlab. The result of the encryption process is 696000 times faster than Matlab. Meanwhile, the decryption process is 236000 times faster than Matlab.
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