A nonprecharged data-bus scheme to enhance the intrinsic read data rate of DRAM cores is proposed. Eliminating the precharge cycle of the DRAM data bus can reduce the unit bit time. A differential ...partial response detection data-bus amplifier is also employed to detect signals on the nonprecharged data bus that are degraded by large intersymbol interference. To enhance the read operation further, column selections are overlapped by interleaved column decoders. To increase the operating margin of the nonprecharged data-bus read, a skew-controlled column-selection pulse generator was developed. An isolated sense-amplifier scheme increases the write data rate of the DRAM core. To verify these schemes, a 4-Mb DRAM was fabricated via 0.24-/spl mu/m DRAM technology. These schemes realized a 500-Mb/s per data-bus read operation and a 100-Mb/s per data-bus write operation without an area penalty.
A partial-response detection technique cuts the driver power by up to 85% in memory-to-processor communication with several hundred MHz data rates. The signaling scheme reduces driver power by ...reducing the transistor width and raising the termination resistance above the the characteristic impedance. This results in a reduction of the signal bandwidth and thus a large inter-symbol interference (ISI). This side effect is offset by detecting the partial response of the transmitted signal, in which the ISI is subtracted from the signal. The receiver samples the data at half-periods of the clock. It employs a delay-locked loop to time sampling at the end of each symbol period of length T, to fully exploit signal current integrated in the signaling line during that period.
A chip-to-chip signaling scheme employs partial response detection (PRD) combined with the zero-delay time delivery of a global timing reference, or global mean time (GMT). High-output-impedance ...drivers and higher termination resistances for signal transmission reduce driver power to the 10 mW range while maintaining a data rate of 500Mb/s. The resulting intersymbol interference (ISI) is eliminated by the PRD receivers, a type of auto-zero-comparator. Signal lines are segmented and pipelined by PRD buffers to limit the segment lengths to below Lmax=cT/2, where c is the effective velocity of signal propagation and T is the bit time. Segmentation reduces the driver power considerably.
500 Mb/s non-precharged data bus for high-speed DRAM Saito, M.; Ogawa, J.; Wakayama, S. ...
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156),
1998
Conference Proceeding, Journal Article
For a DRAM core with bandwidth per memory more than one order of magnitude higher than the current DRAMs without increasing the number of internal busses and the area and power they require, the data ...rate per DRAM must be increased. This nonprecharged bus combined with a bus amplifier that employs partial response detection (PRD) achieves 500Mb/s data-bus rate for read, 2.5 times larger than that of a conventional DRAM core. The isolated sense amplifier (ISSA) realizes more than 400 Mb/s data-bus data rate for write. Due to the intrinsic high data-rate of the bus, no core interleaves and no increase in the number of buses is needed to achieve the high-core bandwidth and high-data locality.
We describe a dynamic reconfigurable baseband signal-processing engine suitable for mobile communications that require short operation latency. Signals are processed using a cluster group, which ...consists of clusters containing heterogenous processor elements (PEs), inter-PE networks, and a sequencer that controls dynamic reconfiguration. The cluster group also has dedicated shared signal processing resources. In the cluster, combined data transfer and operations are carried out within one cycle to minimize operation latency, except for the multicycled PE. We evaluated the architecture by mapping several physical-layer IEEE802.11a and 11b wireless LAN algorithms. The results confirmed a shorter processing latency.
