By exploiting the triple-well option available in a deep-submicron CMOS process, we developed monolithic active pixel sensors (MAPS) with the unique features of full analog signal processing and ...digital functionality implemented at the pixel level. After briefly reviewing the results achieved with the first prototype chip, we report on the extensive measurements on the second prototype, containing both single-channel sensors, with an improved noise figure, and an
8
×
8
pixel array. For the pixel having a collecting electrode area of
900
μ
m
2
we measured an equivalent noise charge of about 40 electrons. Using the
Fe
55
5.9
keV line, we obtained a Signal-to-noise (S/N) ratio of about 30. The pixel matrix
(
50
×
50
μ
m
2
)
has been successfully readout up to 30
MHz. Through noise scans, an expected significant threshold dispersion has been measured.
The measurements presented in this paper confirm the capability of our MAPS, based on the deep n-well concept, to be operated as ionizing radiation detectors and suggest a series of improvements we are already implementing in the design of the next prototype chip.
The front-end chip of the SuperB SVT detector Giorgi, F.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
Journal Article
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The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier ...B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.
Beam test results for the SuperB-SVT thin striplet detector Fabbri, L.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
Journal Article
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The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45° angle to the ...detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.
Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the ...full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.
Ratios of the ψ′ over the J/ψ production cross sections in the dilepton channel for C, Ti and W targets have been measured in 920 GeV proton-nucleus interactions with the HERA-B detector at the HERA ...storage ring. The ψ′ and J/ψ states were reconstructed in both the μ+μ- and the e+e- decay modes. The measurements covered the kinematic range -0.35≤xF≤0.1 with transverse momentum pT≤4.5 GeV/c. The angular dependence of the ratio has been used to measure the difference of the ψ′ and J/ψ polarization. All results for the muon and electron decay channels are in good agreement: their ratio, averaged over all events, is Rψ′(μ)/Rψ′(e)=1.00±0.08±0.04. This result constitutes a new, direct experimental constraint on the double ratio of branching fractions, (B′(μ)B(e))/(B(μ)B′(e)), of ψ′ and J/ψ in the two channels. The ψ′ to J/ψ production ratio is almost constant in the covered xF range and shows a slow increase with pT.
The high luminosity asymmetric e + e - collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 10 36 cm -2 s -1 with moderate beam currents and ...a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 μm in both coordinates, low material budget (<;1% X 0 ), and able to withstand a hit background rate of several tens of MHz/cm 2 . The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.
We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a ...CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely "APSEL3T1" and "APSEL3T2". The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55 Fe and electrons from 90 Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip "APSEL4D", having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.
The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This ...paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.
The spin-parity analysis of the reactions
pp → π
+π
−π
0,K
+K
−π
0,K
±K
0π
∓
is performed in the context of an approach which solves the problems connected to the complexity of
K
+
K
−
π
0 dynamics ...and to the number of partial waves involved in
pp
annihilation at rest. The preliminary results are presented.
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