Compact and high current inductors determine the power density and efficiency of voltage regulators (VRs) for computing ICs. Conventional moulding structures using powder cores and gapped ferrite ...cores are reaching the limits of size miniaturization. In this paper, a sandwich-structured inductor using 2D magnetic nanocrystalline flake ribbon (NFR) is developed to achieve high current density and low height. The analytical models of inductance and conduction losses are developed and validated by finite element methods and experiments. A 5 to 1 V, 50 A, VR is built to compare the performance of the fabricated NFR sandwich inductor to the latest commercial counterpart. Thermal performance is investigated, stability tests under solder iron heat and reflow temperature are performed. The fabricated sandwich inductor is featured as simple structure, low profile, low DC resistance (DCR), high saturation current, soldering heat stable, but in the modest compromise of the AC conduction and core losses.
Coefficients of thermal expansion (CTE) of various materials in packaging structure layers vary largely, causing significant thermomechanical stress in power electronic packages during operation. For ...wirebondless SiC modules, the stress is even larger due to the structure's rigidity and the high Young's modulus of SiC crystals. This letter takes a flexible printed circuit board (FPCB)/die/active metal brazed (AMB) packaging stack as an example to prove the feasibility of floating die structure enabled by liquid metal (LM) fluidic connection. The CTE mismatch among the die, printed circuit board, and AMB substrate is decoupled by the LM layer without compromise of thermal and electrical conduction. The finite-element analysis demonstrates a 56% reduction in von Mises stress of the device and more than 99% shear stress reduction at the FPCB-AMB interface, compared with a conventional rigid solder connection. Testing results show that LM-based packaging has a similar thermal and electrical conduction and higher breakdown voltage when compared with the soldered counterpart. Accelerated thermal cycling aging tests validate the stability of the insulation ring for LM-based packaging, especially under high-temperature conditions. The feasibility of using LM fluidic interconnections for a floating die structure of SiC packaging is validated.
Employing high switching speed wide bandgap (WBG) devices improves the efficiency of industrial drive inverters, but can result in motor overvoltages for shorter lengths of cable between the inverter ...and motor. These overvoltages are caused by high frequency impedance mismatches resulting in reflection of the voltage pulse edges of the inverter output. Forwards and backwards travelling reflections interfere and in the worst case cause double the DC-link voltage to appear across the motor terminals. In this paper this doubling of the motor voltage stress is observed with only a 10 metre cable. To mitigate the motor overvoltage a novel method using a differential mode coupled inductor between the paralleled half bridges and the phase output is proposed. By adding a delay time between the half bridges at every switching event a quasi-three-level output is produced which can actively cancel reflected voltage waves, eliminating the cause of motor overvoltages. The method can be utilised for three phase inverters, and when using independently driven paralleled devices only requires one additional inductor per phase. A design process for the coupled inductors is given which aims to minimise the circulating current between the half bridges and therefore give minimal increase in conduction losses due to imbalanced current sharing. These additional conduction losses and other limitations of the proposed method are analysed. An inverter utilising this proposed method is implemented and compared to a passive filter designed for overvoltage mitigation. The novel method achieves near perfect overvoltage mitigation with much smaller additional volume and much lower losses than the filter. Furthermore the losses when using the active mitigation method are very similar to using the inverter with no overvoltage mitigation.
In an effort to reduce switching loss, increase switching frequencies, and shrink passive component sizes, power device switching times are being pushed into nanosecond and subnanosecond intervals. ...However, these fast switching times require high rates of change of current making the power devices susceptible to overvoltage damage from parasitic inductance in the power loop. This presents challenges in measuring the device switching current accurately and, in turn, makes accurate measurements of device switching energy and stored charge difficult. Traditional current measurement methods either do not have the required frequency response to view the switching edge accurately or have a high parasitic inductance that can significantly alter switching performance and cause damage to the power device. In this article, an active current measurement system is developed. This circuit achieves up to 1.6-GHz bandwidth with zero overshoot. By utilizing mutual inductance cancellation, an insertion inductance down to 20 pH has been achieved. The research performed in this article thereby allows for an accurate measurement of device switching loss with minimal power circuit disturbance. The performance of this current measurement is experimentally verified in the frequency domain using a vector network analyzer, and time-domain switching measurements are compared with state-of-the-art current measurement.
Parallel connection of GaN high-electron-mobility transistors (HEMTs) is a more cost-effective or even an unavoidable solution to achieve higher current ratings. As the load decreases, the switching ...loss of paralleled HEMTs becomes dominant over the conduction loss, and the overall power conversion efficiency drops sharply. To reduce the light-load switching loss, this article proposes a desynchronizable paralleling scheme. The midpoint (ac terminal) of each paralleled HEMT half bridge is connected with a commutation inductor, which thus, enables two operation modes-synchronous and asynchronous modes. The synchronous mode is activated at heavy loads to share the high current; the added commutation inductors lead to better current sharing than the direct parallel. When operating at light loads, however, the paralleled devices are desynchronized to generate a circulating current flowing through the commutation inductors. The circulating current enables the lagging HEMTs to achieve the zero-voltage switching and allows the leading ones to turn on at a current lower than the load, thereby significantly reducing the total switching loss. In addition, a thermal balancing scheme is proposed to alleviate the thermal stress imbalance between the desynchronized GaN HEMTs. The operating principle and design guidelines of the desynchronizable paralleling scheme are detailed. Finally, experimental results from multipulse and continuous tests of GaN HEMTs are provided to verify the advantages of the proposed paralleling scheme in reducing light-load switching loss and improving light-load efficiency.
This article proposes a positively coupled inductor (PCI) based paralleling scheme for basic semibridge switching cells, which are formed by power MOSFETs and diodes. Both the semibridge switching ...cells and the inductors are split into two parallel parts, and thus, a small differential mode (DM) inductance is formed between the midpoints of the parallel semibridge switching cells. A time-delay-based modulation strategy is applied to generate a controllable circulating current, which enables all active switches to achieve the zero-current switching (ZCS) or zero-voltage switching, and all diodes to achieve ZCS turn- off . Accordingly, the switching loss and the reverse-recovery loss can be significantly reduced. The operating principle of the proposed paralleling scheme is characterized by two complementary operation modes: desynchronized mode with soft-switching (lower switching loss) and synchronized mode with lower conduction loss. Compared with conventional soft-switching schemes, this solution features zero auxiliary switches, constant switching frequency, and improved full-power-range efficiency enabled by the dual operation modes. Furthermore, design guidelines of the PCI are presented where a novel winding arrangement is proposed and verified to obtain a controllable DM inductance. The operation principles and advantages of the proposed paralleling structure are comprehensively validated on both buck and boost dc-dc converters with Si/SiC power MOSFETs and diodes.
State-of-the-art soft-switching modulations such as critical conduction mode and triangular current mode increase the conduction loss of power semiconductors and require variable switching ...frequencies; thus, these soft-switching methods are seldom used in high-power dc-ac conversion. To achieve soft-switching while maintaining low root mean square currents, this article proposes a hybrid quadrilateral and continuous current mode (HQCCM) modulation for general high-frequency single-phase dc-ac conversion based on paralleled silicon carbide metal oxide semiconductor field-effect transistors. The proposed HQCCM adaptively operates in soft-switching quadrilateral current mode or hard-switching continuous conduction mode in one ac line cycle depending on the instantaneous ac load current. Thus, high efficiencies can be achieved over the full power range. This HQCCM modulation features adaptive soft-switching, constant switching frequency, and compatibility to line filter and is applicable for high-power applications. A 4.4-kW single-phase dc-ac inverter is developed and tested to verify the advantages of the HQCCM. This article is accompanied by a video demonstrating the effectiveness of the proposed HQCCM in varying load scenarios.
Zero voltage switching (ZVS) is useful to increase power electronics efficiency but difficult to achieve due to the non-linear parasitic capacitance of the power semiconductors and varying load ...current. This letter proposes a self-adaptive ZVS method by using the intrinsic electroluminescence (EL) property of SiC MOSFETs to automatically adjust the switching frequency in every switching cycle to retain the optimal ZVS in varying load current. A sensing circuit is developed to digitally utilize the EL to trigger ZVS and embodied in a customized PCB-embedded half-bridge power module. Experimental results demonstrate the effectiveness of the proposed optically-triggered self-adaptive ZVS in a Buck converter. The proposed method is compatible with conventional PWM gate drives for various power electronic devices and applications.
This paper introduces a toroidal nanocrystalline powder core with a trapezoidal cross section. The non-uniform magnetic flux distribution of toroidal cores with different cross sectional geometries ...is discussed, the inductance equations are derived, and the geometrical optimisation factor is given in order to retain the highest possible inductance value whilst minimising material usage. A 10-turn coil is wound on the core, with the measured inductance values showing a good match with both FEM and mathematical calculation. The near-field electromagnetic interference (EMI) radiation in close proximity to the inductor is investigated by both FEM and experimental validation, and the toroidal core with a trapezoidal cross section has shown reduced EMI. By adopting a trapezoidal cross section for the toroidal core, a 30 % reduction in material usage and lower EMI are achieved, albeit with a compromise of 14% in inductance.
This article proposes a new power electronic packaging for discrete dies, namely, a standard cell, which consists of a step-etched active metal brazing (AMB) substrate and a flexible printed circuit ...board (flex-PCB). The standard cell exhibits high thermal conductivity, complete electrical insulation, and low stray inductance, thereby enhancing the performance of SiC mosfet devices. The standard cell has a stray power loop inductance of less than <inline-formula><tex-math notation="LaTeX">\text{1}\,\text{nH}</tex-math></inline-formula> and a gate loop inductance of less than <inline-formula><tex-math notation="LaTeX">\text{1.5}\,\text{nH}</tex-math></inline-formula>. The standard cell has a flat body with surface-mounting electrical connections on one side and direct thermal connections on the other. The use of flex-PCB die interconnection enables maximum utilization of source pads while providing a flexible gate-source connection and the converter PCB. This article presents the design concept of the standard cell and experimentally validates its effectiveness in a converter system.
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