In this paper we show that discrepancies that were occasionally observed in the base current mismatch area scaling of a 0.25 /spl mu/m BICMOS technology are due to a new mismatch phenomenon. We ...discuss how the cause of the effect was identified through electrical and TEM device analysis. These analyses helped to spot and solve a potential yield limiter in the technology.
In this paper we present an approach to provide insight in electrical parameter shifts due to mechanical stress by means of mechanical modelling through FEA. A fast assessment of the expected ...parameter shift as a function of location and current direction with respect to stressors can directly be made using the FEA tool. Additionally the results can be exported for usage in electrical circuit simulation tools such as Cadence ADE. The link with such tools enables a more detailed investigation into the effects of stress on parts of the circuit and potential amplification of small shifts. Simulated results based on a test case involving solder bump induced stress are compared with measurements on dedicated high resolution test chips. The measurements show a good correlation with the simulation results, both qualitatively and quantitatively.
This paper discusses in detail how standard bench-top semiconductor parameter analyzers can be used for characterizing low frequency noise of semiconductor devices. We demonstrate that flicker noise ...of MOSFETs and bipolar transistors can be characterized without any additional instrumentation hardware such as low-noise amplifier, filters, or signal analyzer. Moreover, this new approach allows independent simultaneous noise assessment at multiple device terminals down to very low frequencies (milli-Herz and lower), and enables noise characterization at much lower device currents (sub-nA) than generally reachable with conventional flicker noise measurement systems.
This paper discusses a new method for characterization of matching of capacitors using the so-called floating gate capacitance measurement method. After an introduction of this measurement method, ...modifications are discussed that were implemented to boost the measurement accuracy and repeatability from its original thousands of ppm's (0.1 to 0.3%) to values as low as 50 ppm (0.005%). Instrumental in these improvements are the introduction of a double slope measurement procedure to compensate for systematic offsets, as well as the use of repeated measurements and averaging to reduce the influence of the measurements system's noise. The improved accuracy, including statistical characterization of the measurement system's short term repeatability, are required for correct determination of capacitor matching of the extremely well-matching double-polysilicon capacitor structures that were used for this study.
A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution ...experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.
Systematic and random parametric mismatches are major performance limiters as well as notorious causes for re-designs of high precision mixed-signal circuits and systems. Therefore it is extremely ...important to measure, analyze, interpret, model and document parametric mismatch mechanisms. This paper provides an overview of the main requirements and techniques for mismatch characterization of active and passive IC devices in mixed-signal technologies.
We present a first successful attempt to use microsecond DC pulses for matching measurements on 65-nm MOS transistors down to low current levels. We demonstrate that the interface states that ...contribute to the mismatch (if they indeed do so) in the weak and moderate inversion region must have charging and discharging time constants below 1 μs.
Using time sampled DC measurements from standard bench-top semiconductor parameter analyzers, it proves possible to characterize low frequency noise of BJT's down to sub-mHz frequencies. The new ...technique is exemplified using SiGeC HBT's. Base current random telegraph noise with time constants of as long as tens of seconds is demonstrated.
This paper discusses a sophisticated backend capacitor mismatch characterization technique based on direct capacitance measurements with a standard C-V meter, wafer prober subsite moves to measure ...the two capacitors of each pair sequentially and monitor the measurement noise, and statistics to take this noise appropriately into account. We describe requirements, capabilities and limitations of this approach. It is concluded that this technique proves excellently suited for assessing the matching performance of backend capacitors in the most relevant range of 10 fF to 10 pF.
Using a dedicated set of - asymmetrically designed - matched pair test structures and a data analysis technique based on so-called mismatch sweeps, we answer some important questions in the ...discussions on variability in advanced CMOS technologies.