Using a dedicated set of - asymmetrically designed - matched pair test structures and a data analysis technique based on so-called mismatch sweeps, we answer some important questions in the ...discussions on variability in advanced CMOS technologies.
A new subsite stepped multiresistor test structure is introduced. This test structure is used for studying and improving small resistance mismatch patterns in resistor ladders for high-resolution ...analog-to-digital converter applications. By utilizing wafer prober subsite movements and contact pad cross connections in the test structures, in combination with a Kelvin measurement method and dedicated statistical data evaluation technique, this approach enables identification of very small (<0.05%) systematic resistance mismatch patterns in realistic high- precision resistor ladder implementation. The most disturbing mismatch pattern was found to be caused by mechanical stress from the resistor ladder head layout, while others are attributed to decananometer scale reticle writing artefacts.
This work quantitatively compares breakdown triggers for constant voltage stress of large area NMOS capacitors (up to 10 mm/sup 2/) with 1.8 to 12 nm gate oxide thickness (with negative V/sub G/). We ...conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation (RMS). We also present data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.
Why and how can parametric mismatch studies help to improve IC-technologies? After an introduction on the importance of parametric mismatch for performance and yield of mixed-signal as well as ...digital technologies, the basic terminology and techniques for BJT mismatch fluctuation assessment are reviewed. Two examples are discussed to demonstrate how parametric mismatch fluctuation studies help to improve better device architecture of poly-emitter BJTs. The ensuing process refinements result in better circuit functionality as well as yield improvements.
High-voltage RF active and passive devices, including LDMOS, fringe capacitors, transformers and inductors with good RF performance, are required for building integrated RF power amplifiers at ...Watt-level in high-performance cost-effective RF front-end ICs. This paper reports, for the first time, a novel 3.3V / 5V RF-LDMOS with a cutoff frequency beyond 100GHz, designed and fabricated without any additional dedicated mask in an advanced sub-28nm node FDSOI process. For passive devices, by combining the novel RF design with an RF-compatible metal stack, accurate EM simulation, and 4-port RF characterization, a record high Q-factor for a 7V-fringe capacitor, a 2-way transformer and 8-shaped inductors are obtained. The RF performance of these high-voltage (HV) capable devices is comparable to best-in-class devices in RF-HV-centric non-CMOS processes, e.g. SiGe and GaAs. This enables highly integrated cost-effective power amplifiers for both WiFi (5GHz) and 5G (28GHz) applications.
In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The effect is used to determine the SOI FinFET thermal impedance and to determine the ...temperature rise during FinFET operation.
This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies. MOSFET matching measurements show that these effects are stochastic ...in nature, and are associated with the gate poly-Si grain size distribution. Moreover, this work demonstrates that these effects can strongly degrade transistor matching performance of future CMOS generations.
This paper discusses test structures and measurements to answer the question of how far mixed-signal circuit designers (and test structure designers) should keep layout asymmetries away from matched ...device constructions. Test structures for assessing the span of mechanical stress asymmetries on matched device constructions were designed, fabricated and characterised. The obtained results can be extremely important for small signal analogue electronic circuit designers.
Effects of metal coverage on MOSFET matching Tuinhout, H.; Pelgrom, M.; Penning de Vries, R. ...
International Electron Devices Meeting. Technical Digest,
1996
Conference Proceeding
Using dedicated MOSFET matching test structures, this paper demonstrates that performance of analog as well as digital circuit blocks can degrade dramatically in multi level metal CMOS processes when ...transistors are covered with metal. An optimized back-end treatment improved the MOSFET matching significantly.
