Analog circuits in ultra-deep-submicron CMOS Annema, A.-J.; Nauta, B.; van Langevelde, R. ...
IEEE journal of solid-state circuits,
2005-Jan., 2005, 2005-01-00, 20050101, Letnik:
40, Številka:
1
Journal Article, Conference Proceeding
Recenzirano
Odprti dostop
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in ...linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.
Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I/sub off/) of MOSFET transistors increases as the ...technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (/spl Delta/V/sub to/) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V/sub t/ mismatch shift. This effect can be so severe that I/sub off/ can increase by more than one order of magnitude with respect to its nominal value due only to V/sub to/ mismatch. We further show through experimental results that the V/sub to/ mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I/sub off/ level as for a V/sub to/ mismatch characterized out of the subthreshold regime.
This paper discusses the challenges of characterization of 1/f noise and its variability under weak-inversion operating conditions of MOSFETs. A dedicated test module was designed with a range of ...MOSFET types with different layout implementations, particularly focusing at the noise behavior of very wide transistors. Through extensive use of a commercial noise characterization system it proved possible to evaluate the variability of 1/f noise in weak-inversion, revealing several interesting and important subtleties of low frequency noise.
We present a study of the temperature dependence of transistor mismatch in a 65-nm CMOS platform over a temperature range of 0degC to 125degC. We show that the relative-drain-current-mismatch ...fluctuation properties improve marginally in strong inversion, while they are strongly affected in the subthreshold region. This is compared and explained with a commonly used model. Furthermore, we analyze the change over temperature of the I ON mismatch of individual matched pairs. This analysis shows, for the first time, that although relative-current-mismatch fluctuation standard deviations estimated on whole populations are reduced at higher temperatures, the current mismatch of individual pairs can change substantially over temperature.
We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates ...interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability.
This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. ...The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.
This paper presents a study on techniques for characterization of metal-oxide-semiconductor field-effect transistor (MOSFET) transconductance mismatch, using matched pairs with intentional 1% ...dimensional offsets. The relevance of this kind of work is demonstrated by the introduction of a new mismatch phenomenon that can be attributed to mechanical strain, associated with metal dummy structures that are required for backend chemical mechanical polishing (CMP) processing steps.
Layout effects (well proximity effect, gate-STI distance effect, litho proximity effects, etc.) can lead to significant deviations between measured and modeled drain currents in advanced CMOS ...processes. Because several of these effects can occur at the same time and because a proper distinction between systematic and random effects is not always made, this often leads to confusion on the subject of variability. Using a dedicated set of-asymmetrically designed-matched pair test structures and a data analysis technique based on so-called mismatch sweeps, we answer some important questions in these discussions on variability in advanced CMOS technologies. Taking the STI-induced stress effect as an example, we show that, although there can be a large systematic offset in drain current and threshold voltage due to this effect, there is no significant impact on random mismatch fluctuations.
In this work we confirm the validity of the Defect-Centric distribution for predicting the CHC behavior, by using a set of more than 1000 nMOSFETs in 45 and 65 nm bulk planar CMOS technologies. The ...use of matching pairs enabled us to determine the intrinsic value of the CHC variability by mitigating extrinsic sources of variability. The average impact of a single charged trap, which is a quantitative indicator of the time-dependent variability, is practically independent of the stress time and stress channel voltage in single devices and in matching pairs, while it increases for a more scaled technology node.
Designing outside rail constraints Annema, A.J.; Nautal, B.; van Langevelde, R. ...
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519),
2004
Conference Proceeding
Odprti dostop
CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower ...supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.
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