In this work, the degradation of the random telegraph noise (RTN) and the threshold voltage (Vt) shift of an 8.3Mpixel stacked CMOS image sensor (CIS) under hot carrier injection (HCI) stress are ...investigated. We report for the first time the significant statistical differences between these two device aging phenomena. The Vt shift is relatively uniform among all the devices and gradually evolves over time. By contrast, the RTN degradation is evidently abrupt and random in nature and only happens to a small percentage of devices. The generation of new RTN traps by HCI during times of stress is demonstrated both statistically and on the individual device level. An improved method is developed to identify RTN devices with degenerate amplitude histograms.
In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate ...off-voltage, the reset gate off-voltage, the photodiode integration time, and the sense node charge retention time. Besides the well-known source follower RTN, we have identified the RTN caused by varying photodiode dark current, transfer-gate and reset-gate induced sense node leakage. These four types of RTN and the dark signal shot noises dominate the noise distribution tails of CIS and non-CIS chips under test, either with or without X-ray irradiation. The effect of correlated multiple sampling (CMS) on noise reduction is studied and a theoretical model is developed to account for the measurement results.
This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1-μ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is ...introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm 2 . This paper achieves a 0.66erms - with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/-0.94 LSB to +0.29 LSB/-0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz.
A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise ...decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model.
This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with threshold voltage cancellation technique for pixel fixed pattern noise (PFPN) reduction. ...A tunable pixel response curve was applied for different environments. To avoid the gain loss of source follower in conventional APS structure, a column shared-amplifier with programmable gain was also applied. A prototype high DR Lin-Log CIS chip consisting of 100 × 100 5-T pixel array with n+/p-sub photodiode, a pixel area of 6 × 6 μm 2 , and 3.3 V operation was designed and fabricated in TSMC 0.18 μm CMOS 1P6M standard process. The measured results achieved a DR of 143 dB, a PFPN related to sensitivity in logarithmic response (rms/log-sensitivity) of 1.96%, and a PFPN related to full-swing in logarithmic response (rms/Vlog-swing) of 0.45%. Linear and logarithmic sensitivity were 651 mV/lux-s and 55 mV per decade of illumination, respectively, at 50 fps. The temporal noise and power consumption were 0.746 m Vrms and 1.88 mW, respectively.
This paper proposes a novel single-slope (SS) ADC design and operation for full well capacity (FWC) expansion of CMOS image sensor to increase the dynamic range for small pixel. With the proposed ...technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared with the general double A/D conversion operation. A 160×140 CMOS image sensor chip with the proposed SS ADC is fabricated using 0.18-μm CMOS image sensors technology. This chip achieves a sensitivity of 5.33 V/lx·s and a FWC expansion ratio of 2.18 at 38.5 fps. The measured FWC is 47.45 ke - with 118% boost. The ADC resolution is 8 bits and the resulting differential nonlinearity/integral nonlinearity of proposed column-parallel SS ADC is (+0.16,-0.24)/(+0.28,-0.52) least significant bit. The column-fixed pattern noise is 0.16%.
A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the ...measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 μs and 500 μs with the median around 10 μs at room temperature.
The effects of X-ray irradiation on the random noises, especially the random telegraph noises (RTN), of a 45-nm on 65-nm stacked CMOS image sensor with 8.3M 1.1 μm pixels are investigated. It is ...found that before X-ray irradiation the dominant type of RTN among the noisiest pixels is the source follower (SF) MOSFET channel RTN. In contrast, after X-ray irradiation up to a total ionizing dose of 1 Mrad(SiO 2 ), the RTN becomes dominated by the variable transfer-gate-induced sense node (SN) leakage. These two different types of RTN can be distinguished by their dependence on the transfer gate (TG) OFF voltage and the time between the correlated double sampling (CDS). The magnitude of the RTN from the variable SN leakage is proportional to the CDS time and can be suppressed effectively by increasing the TG OFF voltage, whereas the SF RTN is independent of the CDS time or the TG OFF voltage.
This paper proposes a dual-exposure single-capture wide dynamic-range (DR) CMOS image sensor (CIS) for optical identification systems. The proposed sensor achieves columnwise highly/lowly illuminated ...pixel detection, and only the "adequate" voltage signal (long- or short-exposure signal) is digitized. With an integrated highly/lowly illuminated pixel detection function in the columnwise single-slope (SS) ADC, each pixel is read out only once with highly or lowly illuminated pixel index for synthesis of a wide DR frame. This approach can dramatically reduce power dissipation compared to existing multiframe-readout solutions. The DR expansion ratio is programmable and depends on the time ratio of long- to short-exposure periods. A 160 × 140 wide DR CIS chip with the proposed SS ADC was fabricated using 0.18-μm CIS technology. This chip achieves a sensitivity of 5.33 V/lx · s and a noise floor of 0.29% of full swing (73e - ) at 60 fps. The measured DR is 91 dB with a 40-dB boost by setting the exposure time ratio as 100. The resulting DNL is +0.16/ - 0.24 LSB, and the column-fixed-pattern noise is about 0.16%.
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