Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are described. Two ...important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic‐level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.
Three‐dimensional resistive switching cross‐bar array memories are highly desirable future memory devices for data centric computation. Issues in the circuitry, integration, and material properties of the two‐ and three‐dimensional crossbar array memories are dealt with in a quantitative manner. The impressive progress in theoretical understanding and fabrication of these devices achieved during the past decade is summarized, and an outlook on possible applications is further provided.
Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are ...critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate vs charge-trap-layer), array-level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell-level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.
The development of a resistance switching (RS) memory cell that contains rectification functionality in itself, highly reproducible RS performance, and electroforming‐free characteristics is an ...impending task for the development of resistance switching random access memory. In this work, a two‐layered dielectric structure consisting of HfO2 and Ta2O5 layers, which are in contact with the TiN and Pt electrode, is presented for achieving these tasks simultaneously in one sample configuration. The HfO2 layer works as the resistance switching layer by trapping or detrapping of electronic carriers, whereas the Ta2O5 layer remains intact during the whole switching cycle, which provides the rectification. With the optimized structure and operation conditions for the given materials, excellent RS uniformity, electroforming‐free, and self‐rectifying functionality could be simultaneously achieved from the Pt/Ta2O5/HfO2/TiN structure.
A feasible method is reported for achieving a highly uniform, electroforming‐free, and self‐rectifying RS memory cell with a two‐layered dielectric structure. HfO2 works as the resistance switching layer by trapping and detrapping the deep 1.0 eV trap sites, whereas Ta2O5 layer remains intact during the switching and forms a high Schottky barrier with a high‐work‐function Pt to constitute the rectifying functionality.
The NAND flash memory serves as the key enabler of the flourishing of portable handheld information devices, such as the cellular phone. The recent upsurge in the sales of vertical NAND flash memory ...(V‐NAND) entails a further increase in the available information capacity at the edge devices and the servers with higher performance and lower power consumption compared with the magnetic hard‐disc drives. Nonetheless, there will certainly be an upper limit for the number of stacked layers, which will be the point at which further memory density increase will stop. While V‐NAND is a supreme outcome of semiconductor memory technologies, it still relies on conventional Si‐based materials. The newly explored memory materials and concepts, such as the resistance‐based memories, can therefore be an appealing contender to or successor of V‐NAND. In this review, the current state of V‐NAND is first briefly looked into, and then the eventual limitation of memory density increase and performance boost are discussed. Most importantly, the possible strategies of integrating the resistance‐based memories into the vertical architecture are then discussed. Finally, the outlook for such resistance‐based vertical memories is presented.
Pathways to overcome the scaling limitation of vertical NAND flash memory (V‐NAND), the present market leading nonvolatile memory, providing new materials and array structure suggestions, are provided. Specifically, the favorable aspects of a vertical resistive random access memory (V‐ReRAM) structure, such as areal density and decoding schemes, are highlighted in comparison with the commercialized nonvolatile memories: 3D‐Crosspoint and V‐NAND.
Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by ...including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric‐field distribution can solve the non‐uniformity issue of future ReRAM.
Various array types of 1‐diode and 1‐resistor stacked crossbar array (1D1R CA) devices composed of a Schottky diode (SD) (Pt/TiO2/Ti/Pt) and a resistive switching (RS) memory cell (Pt/TiO2/Pt) are ...fabricated and their performances are investigated. The unit cell of the 1D1R CA device shows high RS resistance ratio (≈103 at 1.5 V) between low and high resistance state (LRS and HRS), and high rectification ratio (≈105) between LRS and reverse‐state SD. It also shows a short RS time of <50 ns for SET (resistance transition from HRS to LRS), and ≈600 ns for RESET (resistance transition from LRS to HRS), as well as stable RS endurance and data retention characteristics. It is experimentally confirmed that the selected unit cell in HRS (logically the “off” state) is stably readable when it is surrounded by unselected LRS (logically the “on” state) cells, in an array of up to 32 × 32 cells. The SD, as a highly non‐linear resistor, appropriately controls the conducting path formation during the switching and protects the memory element from the noise during retention.
1 diode 1 resistor (1D1R) resistive memory devices with the crossbar array configuration composed of a stacked Schottky diode (Pt/TiO2/Ti/Pt) and unipolar resistive (URS) memory (Pt/TiO2/Pt) elements are fabricated, and their fluent functionality is proven. Atomic force microscopy is used to image one memory cell and scanning electron microscopy is used to study the 32 × 32 memory array.
Purposes
Previous studies have suggested that there is an increased risk of osteoporotic fracture in gastric cancer survivors. However, the data was not classified according to surgery type. This ...study investigated the cumulative incidence osteoporotic fracture (OF) in gastric cancer survivors according to treatment modality.
Methods
A total of 85,124 gastric cancer survivors during 2008–2016 were included. The type of surgery was classified as total gastrectomy (TG,
n
= 14,428)/subtotal gastrectomy (SG,
n
= 52,572)/endoscopic mucosal dissection and endoscopic mucosal resection (ESD/EMR,
n
= 18,125). The site of osteoporotic fractures included the spine, hip, wrist, and humerus. We examined cumulative incidence using Kaplan–Meier survivor analysis and cox proportional hazards regression analysis to determine the risk factor of OF.
Results
The incidence of OF per 100,000 patient year was 2.6, 2.1, 1.8 in TG, SG, ESD/EMR group. The cumulative incidence rate was 2.3% at 3 years, 4.0% at 5 years, and 5.8% at 7 years in gastrectomy group, and 1.8% at 3 years, 3.3% at 5 years in the SG group, and 4.9% at 7 years postoperatively in ESD/EMR group. TG increased the risk of OF compared to patients who underwent SG (HR 1.75, 95% confidence interval CI 1.57–1.94), and ESD/EMR (hazard ratio HR 2.23, 95% CI 2.14–2.32).
Conclusion
Gastric cancer survivors who underwent TG had an increased osteoporotic fracture risk than did SG or ESD/EMR in these patients. The amount of gastric resection and accompanying metabolic changes seemed to mediate such risk. Additional research is needed to establish an optimal strategy for each type of surgery.
Herein, a robust programmable stochastic weight generation method for a memristive neural network is proposed. There have been few prior algorithm suggestions for crossbar neural network‐based ...stochastic learning; however, there has not been much attention focussed on robust physical implementations. As a result, coming up with a robust method to provide the probability generator is an essential knob for its physical implementation. Here, implanting such stochastic behavior into the weight update signal itself is proposed, by multiplying it with the randomized probability sequence. To generate such probability sequence, bang‐bang dithering of a phase‐locked loop (PLL) with a binary phase detector (PD) is used. The programmable probability is enabled by introducing an offset for the PD outputs. Yet the dithering sequence has deterministic nature, phase noise of complementary metal–oxide–semiconductor (CMOS) ring oscillator to randomize the deterministic dithering is exploited. As a result, this lower power oscillator offers a better probability sequence, which enables an ultralow power circuit implementation.
A probability generator dedicated for stochastic learning in memristor cross‐point array‐based neural network is presented. It mainly utilizes the intrinsic noise of a complementary metal–oxide–semiconductor (CMOS) ring oscillator, which not only benefits from a robust and practical solution but also from an ultralow power consumption in comparison to the methods proposed in prior works.
3-D integrations are unavoidable task for new emerging memories, including resistive switching random access memory (RRAM), in order to overcome the market leading nand flash. However, an RRAM ...crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a 32 × 32 × 8 vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA.
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