Abstract
This paper designs a simple system that can include electronic clock and stopwatch based on FPGA(Field Programmable Gate Array) and VHDL(Very-High-Speed Integrated Circuit Hardware ...Description Language). The first chapter briefly introduces the research background. The second chapter introduces the theoretical basis of digital circuits and the hardware and software platform used in this paper. In the third chapter, the design of each sub-module of the system and the overall design of the system are carried out. This chapter is the core chapter of this article, which describes the functions of the module and explains the input and output ports. In this chapter, a core point of digital circuit design is reflected: combining modules that realize simple functions into modules that can realize complex functions. And integrate sub-modules that realize similar functions into a top-level module. The fourth chapter is the logic synthesis of the circuit. The fourth chapter shows the simulation of the core module function and the simulation of the system output. The conclusion section summarizes the interesting parts of the design of this paper.
The paper emphasized on the design and application of LDPC coding system using FPGA. The LDPC decoder is used to decode the information/data received from the channel after correcting channel errors ...based on parity bits selection of the data bits. In the communication system, when a parity check failure is noticed, the information from the multiple parity bits can be used to recover the original data bit. The LDPC decoder implementation is done using Shift-Register based design to reduce the complexity. The Modified Sum Product (MSP) method is used to decode, the signal. The system performance is also analyzed with hardware chip and timing parameters with FPGA implementation of the same system. The chip design of the LDPC chip is done usingVivado 17.4, programmed with the use of VHDL and hardware performance is estimated on Virtex-5 FPGA.
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk ...mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i. Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i AbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i. Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement ...the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.
VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic ...SAP-CPU based on VHDL language, which includes the format of control instruction, instruction set, addressing method, test program and the architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.
SoC is the ASICS (ApplieationSpeenIetgratdeCierulst) design methodology of the new technology, refers to the embedded system as the core technology used in PI-based, set of software and hardware in ...one, and the pursuit of products inclusive of the largest integrated system chip. The article in-depth exploration into the complexity of using VHDL language and system programmable logic device (CPLD) to develop "system-on-chip (SoC)" - such as adaptive frequency measurement accuracy of the basic methods to overcome the system of the previous frequency measurement accuracy is not high , measuring the accuracy of the process of change, approaching the speed of slow-type shift shortcomings.
The aim of the paper is to study the applicability of several open-source software products in digital electronics education. Specific examples of typical digital circuits are presented. Examples are ...presented using open-source software for synthesizing logic circuits, testing digital blocks implemented in VHDL. Simulation studies are presented, through which it is easier for students to understand the reasons for incorrect operation of a logic circuit when a malfunction is present.
The study of programmable logic devices (PLDs) is one of the more accessible branches of microelectronics, given the conceptual simplicity and relative ease with which implementation resources can be ...found that enable fairly large projects to be undertaken. The Circuit and Electronic Systems Design course-offered as part of the telecommunication engineering study plan at the Polytechnic University of Valencia, Valencia, Spain-teaches digital design methods based on PLDs. This subject implies an understanding of structures and resources and design methods based on hardware description languages (HDLs). Given the broad and essentially practical nature of the course, it was decided to develop new resources to aid active classroom teaching. These resources include material for self-teaching so that the student can acquire practical design skills when working away from the classroom. A procedure has been designed for student evaluation that is based on moderately difficult practical designs that have been developed using design tools and logical synthesis. This methodology provides added motivation for students as they find themselves tackling real problems associated with digital design. Evaluation is structured around three methods: completely specified designs, partially specified designs, and hardware-oriented physical implementation
This paper presents the current stage of development of a fast Fourier transform (FFT) processor in VHDL. This processor uses fixed-point as numeric representation, taking advantage of the facilities ...provided by the IEEE fixed point package. Its main advantages is that it is being developed as fully parameterizable processor, in a way that the number of bits, fixed point position and number of points computed in the FFT can be easily changed. It is also able to be used in several applications such as classification algorithms and communications systems. An open source prototype core has been developed and it can perform a complete FFT transform using radix-2 with decimation in time. Results and details of this implementation are presented.
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