Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers ...provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar's implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.
Feistel Ciphers Based on A Single Primitive TSUJI, Kento; IWATA, Tetsu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,
2024, 2024-00-00
Journal Article
Recenzirano
Odprti dostop
We consider Feistel ciphers instantiated with tweakable block ciphers (TBCs) and ideal ciphers (ICs). The indistinguishability security of the TBC-based Feistel cipher is known, and the ...indifferentiability security of the IC-based Feistel cipher is also known, where independently keyed TBCs and independent ICs are assumed. In this paper, we analyze the security of a single-keyed TBC-based Feistel cipher and a single IC-based Feistel cipher. We characterize the security depending on the number of rounds. More precisely, we cover the case of contracting Feistel ciphers that have d ≥ 2 lines, and the results on Feistel ciphers are obtained as a special case by setting d = 2. Our indistinguishability security analysis shows that it is provably secure with d + 1 rounds. Our indifferentiability result shows that, regardless of the number of rounds, it cannot be secure. Our attacks are a type of a slide attack, and we consider a structure that uses a round constant, which is a well-known counter measure against slide attacks. We show an indifferentiability attack for the case d = 2 and 3 rounds.
Lightweight ciphers are essential for secure communication in resource-constrained devices. The objective of this research is to implement lightweight ciphers in hardware; and optimize and model ...their design metrics. Design metrics are measured by advanced design flow which includes implementing ciphers in hardware and conducting simulations. To achieve the stated objective, the presented study selects one representative cipher–namely the KATAN/KTANTAN algorithms–to be modeled, implemented and optimized on specific hardware technology; the Field Programmable Gate Array (FPGA) platform. Various designs are implemented to exercise numerous options e.g. block sizes, number of implemented rounds and key scheduling. Then, design metrics are measured and modeled.
In general, results demonstrate that number of resources and measured power consumption exhibit similar, but not identical, profile against design options. Measured energy trends are more complex. Specifically, results show that employing variable key scheduling increases resources, power and energy by 30%, 42% and 58%, respectively. Further, increasing the block size by 50% increases resources and power by about 53% and 55% respectively, but reduces energy by an average of 10%. Doubling number of implemented rounds in hardware increases resources and power by an average of 43% and 38% respectively. Optimum energy per bit design is produced in the designs with small block size (i.e. 32-bit) in the cases when number of implemented rounds equals to 32 or 64 rounds. When the energy and area design requirements are to be balanced, the optimum design is the 16-round implementation. Furthermore, developed models are tested on HIGHT cipher and demonstrate good accuracy.
•Study the structure of lightweight ciphers and select a candidate representative cipher.•Design and optimize the hardware implementation of the representative cipher.•Test various design options like block sizes and number of implemented rounds.•Derive models for speed, resources, and power/energy from the implemented designs.•Apply the derived models on a different cipher for evaluation.
ARIA is a block cipher proposed by Kwon et al. at ICISC 2003 that is widely used as the national standard block cipher in the Republic of Korea. Herein, we identify some flaws in the quantum rebound ...attack on seven‐round ARIA‐DM proposed by Dou et al. and reveal that the limit of this attack is up to five rounds. Our revised attack applies to not only ARIA‐DM but also ARIA‐MMO and ARIA‐MP among the PGV models, and it is valid for all ARIA key lengths. Furthermore, we present dedicated quantum rebound attacks on seven‐round ARIA‐Hirose and ARIA‐MJH for the first time. These attacks are only valid for the 256‐bit key length of ARIA because they are constructed using the degrees of freedom in the key schedule. All our attacks are faster than the generic quantum attack in the cost metric of the time–space tradeoff.
Hash functions are widely used in information security, including commitment schemes, zero‐knowledge proofs, integrity checks, and blockchain technology. However, a thorough analysis of their quantum security under different quantum computing environments is missing. To this end, researchers performed detailed quantum security analysis of reduced‐round block cipher‐based (ARIA) hash functions in different significant modes of quantum computing applications. Their analysis helps us understand the security of hash functions, which has significant implications in information security.
With the advent of advanced technology, the IoT has made possible the connection of numerous devices that can collect vast volumes of data. Hence, the demands of IoT security is paramount. ...Cryptography is being used to secure the authentication, confidentiality, data integrity and access control of networks. However, due to the many constraints of IoT devices, traditional cryptographic protocols are no longer suited to all IoT environments, such as the smart city. As a result, researchers have been proposing various lightweight cryptographic algorithms and protocols to secure data on IoT networks. This paper discusses state-of-the-art lightweight cryptographic protocols for IoT networks and presents a comparative analysis of popular contemporary ciphers. In doing so, it has classified the most current algorithms into two parts: symmetric and asymmetric lightweight cryptography. Additionally, we evaluate several recently developed block cipher and stream cipher algorithms in terms of their security. In the final section of this paper, we address the changes that need to be made and suggest future research topics.
•We first discuss essentiality of security for resource constrained IoT networks. We also discuss the IoT architectural model and various threat according to the IoT environment.•We then classified the most recent developed algorithm into two parts and evaluate recently developed block cipher and stream cipher algorithms in terms of security.•We also present a comparative study of recently proposed IoT-related state-of-art security ciphers.•Finally, we discuss some future challenges for security ciphers that need to be addressed in the future.
It has been challenging work to identify block ciphers under CBC mode over the past few decades. But we can still conduct the identification of block ciphers under CBC mode if enough ciphertext ...streams are available. In this paper, we consider the identification of 5 frequently used block ciphers, AES, DES, 3DES, RC5 and Blowfish. For multi-class identification, the identification rate of 5 block ciphers can reach above 90% as long as the size of ciphertext file is larger than 100 KB when same key and same IV for training and testing ciphertext files. For one to one identification, we identify AES from other 4 block ciphers on condition of different keys or different IVs for training and testing ciphertext files. We can obtain an identification rate of above 97% when the size of ciphertext file is equal to 100 KB. Besides, even if the size of ciphertext file is only 4 KB, the average identification rate is still higher than 80%.
Summary
This paper proposed a hardware architecture of a strong block‐cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based ...on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high‐level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S‐box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA‐Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works.
This paper proposed a hardware architecture of a strong block‐cipher system for digital image encryption and decryption. A PRNG based on two 3D chaotic systems is created to produce strong keys. While, the algorithm performs image encryption through three processes: pixels values hiding, pixels positions hiding, and pixels substitution. To increase the complexity, R rounds of encryption are performed. The hardware cryptosystem is implemented on an FPGA‐Zynq board maintaining a frequency of 156.813 MHz and high throughput of 20,072.064 Mbps.
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