The most promising approach for improving the electrical performance of connectors used in semiconductor test sockets involves increasing their electrical conductivity by incorporating ...one-dimensional (1D) conductive materials between zero-dimensional (0D) conductive materials. In this study, FeCo nanowires were synthesized by electroplating to prepare a material in which 1D materials could be magnetically aligned. Moreover, the nanowires were coated with highly conductive Au. The magnetization per unit mass of the synthesized FeCo and FeCo@Au nanowires was 167.2 and 13.9 emu/g, respectively. The electrical performance of rubber-based semiconductor connectors before and after the introduction of synthetic nanowires was compared, and it was found that the resistance decreased by 14%. The findings reported herein can be exploited to improve the conductivity of rubber-type semiconductor connectors, thereby facilitating the development of connectors using 0D and 1D materials.
Semiconductor devices are tested within a complex environment including a loadboard and a socket. In this paper, we propose a calibration methodology and a RF de‐embedding technique that allows the ...extraction of the device parameters. This method is based on the utilization of several calibration elements inspired by the TRL method. This study has been applied on an active device and the results have been validated using a real test solution.
The most challenging applications for thermal interface materials where durability and thermal performance are both required is found in the semiconductor test and burn-in market. There are a wide ...range of application requirements given the different types of test sockets, test heads, and test equipment configurations. However, a dominant characteristic is the need for a single TIM, applied to a test device, to contact and release cleanly and without damage to either the TIM or to the device under test (DUT), ideally with the ability to conduct such cycles hundreds and thousands of times before replacement of the TIM is required. This places a significant burden on material design, to achieve substantial durability in harsh usage circumstances, while also providing a high level of thermal performance. A mechanical reliability test program for evaluating durability as well as thermal resistance performance of specialized thermal interface materials (TIMs) has been developed. These specialized TIMs have been developed specifically to meet requirements for semiconductor test and burn-in requirements, which are extreme; cycling with multiple contacts for a single TIM (up to thousands of cycles) is a long-sought development goal for the semiconductor test equipment industry.An automated, servo-driven TIM test stand developed to follow industry-standard test methodology is used to conduct testing under controlled test conditions. Examples of test requirements are given, as well as a description of an automated contact cycling test designed to test per those requirements, with results for a set of newly-developed TIMs explicitly adapted for semiconductor test usage. Four test phases have been developed with increasingly challenging test requirements for durability while also exhibiting excellent thermal performance.
We present an optimal test resource allocation strategy using uncertainty reduction in an environment where resource capacity changes dynamically according to engineering activity. The dynamics of ...test capacity change are modeled using a linear programming model and then extended and generalized to a Markov decision process. We analyze the model to develop structural results and illustrate its behavior with numerical examples. To the best of our knowledge, this model is the first to define, formalize, and analyze the decision-making process associated with reducing final test time in an environment where capacity may be dynamically increased, depending on engineering activity results.
This paper discusses characteristics unique in the two-phase high-frequency-testing (HFT) environment in semiconductor manufacturing. We believe this paper is the first to define, formalize, and ...analyze the decision making problem associated with the two-phase HFT. Specifically, this paper defines the problem of minimizing the total HFT capacity usage by systematically finding the optimal number of preliminary HFT bin-1 chips subject to the main HFT, with the existence of the target service rate. We also propose a heuristic algorithm that exploits the special structure of the problem for efficiently obtaining a near-optimal solution. Finally, a numerical analysis and a case study have been conducted to gain more insights on the problem structure and the proposed algorithm.
Within the semiconductor manufacturing chain the automated testing steps are coming increasingly into focus. Delivering enhanced functionality per IC is expected, with the costs per die being ...reduced, while, at the same time, the costs of semiconductor electrical tests increase disproportionately. In addition, the requirements for quality are significantly growing, in general, and in particular, being ensured by automated testing. Hence, the execution of test development and test method quality are becoming an important, competitive-advantage topic. This paper presents a case study that evidences such advantage by adopting software engineering methodologies in test program generation. A software cost model applied to test program development parameters, assessed in combination with Bayesian analysis and Gaussian statistical methods, is discussed in detail. Furthermore, the results obtained indicate the effectiveness of the proposed approach, evidencing a remarkable effort reduction, and address quality robustness in semiconductor test engineering.
Semiconductor test scheduling problem is a variation of reentrant unrelated parallel machine problem considering multiple resources constraints, intricate {product, tester, kit, component} ...eligibility constraints, and sequence-dependant setup times, etc. A multi-step reinforcement learning (RL) algorithm called Sarsa(λ,k) is proposed and applied to deal with it. Allowing enabler reconfiguration, the capacity of the test facility is expanded and scheduling optimization is performed at the component level. In order to apply Sarsa(λ,k), the scheduling problem is transformed into an RL problem by defining state representation, constructing actions and the reward function. Experiments show that Sarsa(λ,k) outperforms the scheduling method in industry and validate the effectiveness of Sarsa(λ,k) to solve the scheduling problem.
Today’s economical cycles challenge the test program generation process for semiconductors with regard to productivity, time-to-market, increasing quality requirements and manufacturing robustness, ...while, at the same time, the complexity of the system-on-a-chip mixed-signal integrated circuits to be tested increases significantly. Furthermore, commercial challenges in combination with competitive advantage become an important factor, not only within semiconductor manufacturing, but also within test program development. This paper provides a review of these challenges, and how they might be addressed. We first give a short introduction and background on semiconductor testing and test development with the focus on mixed-signal and systems-on-chip. This is followed by current roadmaps and considerations for test program software development. Based on the highlighted strength and weaknesses of the reviewed approaches, the authors conclude with some recommendations to address these challenges by adopting software engineering methods for the test program development process.
Web service is a trend of new technology that it is able to support function to user over the internet. That is, user can operate and process the system, and set up values to the machine using the ...internet at the distance location. User doesn't have to have any database for their works in the web service environment. Therefore, the development method has changing from traditional process, it needs mechanical parts with stand-only computer and no network, to service based system with network. In this paper, we propose a service component model for semiconductor test equipment, IC test handler. This model constructs to compose the software component, business logic, as a service.
This paper proposes and evaluates two Petri net-based hybrid heuristic search strategies and their applications to semiconductor test facility scheduling. To reduce the setup time, such as the time ...spent to bring the test facilities to the required temperatures, scheduling multiple lots for each job type together is desirable. Petri nets can concisely model multiple lot sizes for each job, the strict precedence constraints, multiple kinds of resources, concurrent activities and flexible routes. To cope with the complexities for multiple lots scheduling, this paper presents two Petri net-based hybrid heuristic search strategies. They combine the heuristic best-first strategy with the controlled back tracking strategy based on the execution of the Petri nets. The obtained scheduling results are compared and analyzed through a small-size test facility. The better algorithm is also applied to a more sizable facility containing types of resources with a total of 79 pieces and 30 jobs. The future work includes the real-time implementation of the proposed method and scheduling results in real industrial settings.
