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Annovi, A.; Beccherle, R.; Beretta, M.; Bossini, E.; Crescioli, F.; Dell'Orso, M.; Giannetti, P.; Hoff, J.; Liu, T.; Liberali, V.; Sacco, I.; Schoening, A.; Soltveit, H. K.; Stabile, A.; Tripiccione, R.; Volpi, G.
2011 IEEE Nuclear Science Symposium Conference Record, 10/2011Conference Proceeding
We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.
