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Lee, Daewoong; Baek, Jaehyeok; Kwon, Hye-Jung; Kwon, Dae-Hyun; Cho, Chulhee; Kim, Sang-Hoon; An, Donggun; Chang, Chulsoon; Lim, Unhak; Im, Jiyeon; Sung, Wonju; Kim, Hye-Ran; Park, Sun-Young; Kim, Hyoung-Joo; Seol, Hoseok; Kim, Juhwan; Shin, Jungbum; Kang, Gil-Young; Kim, Yong-Hun; Kim, Sooyoung; Park, Wansoo; Kim, Seok-Jung; Lee, Chan-Yong; Lee, Seungseob; Park, Tae-Hoon; Oh, Chi-Sung; Ban, Hyodong; Ko, Hyungjong; Song, Hoyoung; Oh, Tae-Young; Hwang, Sang-Joon; Oh, Kyung-Suk; Choi, Jung-Hwan; Lee, Jooyoung
IEEE journal of solid-state circuits, 01/2023, Letnik: 58, Številka: 1Journal Article
This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.
