The paper emphasized on the design and application of LDPC coding system using FPGA. The LDPC decoder is used to decode the information/data received from the channel after correcting channel errors based on parity bits selection of the data bits. In the communication system, when a parity check failure is noticed, the information from the multiple parity bits can be used to recover the original data bit. The LDPC decoder implementation is done using Shift-Register based design to reduce the complexity. The Modified Sum Product (MSP) method is used to decode, the signal. The system performance is also analyzed with hardware chip and timing parameters with FPGA implementation of the same system. The chip design of the LDPC chip is done usingVivado 17.4, programmed with the use of VHDL and hardware performance is estimated on Virtex-5 FPGA.