We present design studies of the DAQ and trigger system (DAT) for the PANDA detector proposed for the new FAIR facility at GSI. The broad physics program of PANDA requires a novel DAT system able to cope with high interaction rates (up to Hz) and to trigger on various event topologies simultaneously. We used SystemC as a modeling platform to investigate candidate architecture for the PANDA DAT system. We simulated the behavior of the complete system with simplified models of all the components. The model covers detector buffers connected via Ethernet to farms of computing nodes constituting two filtering levels and an event building level. We present results from modeling illustrating the impact of the key architectural choices and parameters on the overall performance.