The concept of the memristor, a resistor with memory, was proposed by Chua in 1971 as the fourth basic element of electric circuitry. Despite a significant amount of effort devoted to the understanding of memristor theory, our understanding of the nonpinched current–voltage (I–V) hysteresis loop in memristors remains incomplete. Here we propose a physical model of a memristor, with a capacitor connected in parallel, which explains how the nonpinched I–V hysteresis behavior originates from the capacitive-coupled memristive effect. Our model replicates eight types of characteristic nonlinear I–V behavior, which explains all observed nonpinched I–V curves seen in experiments. Furthermore, a reversible transition from a nonpinched I–V hysteresis loop to an ideal pinched I–V hysteresis loop is found, which explains the experimental data obtained in C15H11O6-based devices when subjected to an external stimulus (e.g., voltage, moisture, or temperature). Our results provide the vital physics models and materials insights for elucidating the origins of nonpinched I–V hysteresis loops ascribed to capacitive-coupled memristive behavior.