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  • Designing outside rail cons...
    Annema, A.J.; Nautal, B.; van Langevelde, R.; Tuinhout, H.

    2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004
    Conference Proceeding

    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.