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Ming, Leng; Ling-yu, Sun
Energy procedia, 2012, 2012-00-00, Letnik: 16Journal Article
VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic SAP-CPU based on VHDL language, which includes the format of control instruction, instruction set, addressing method, test program and the architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.
