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Measuring the weighted power of CMOS latching circuitsRaič, DušanSource: Informacije MIDEM : časopis za mikroelektroniko, elektronske sestavne dele in materiale = časopis za mikroelektroniku, elektronske sastavne dijelove i materijale = journal of microelectronics, electronic components and materials. - ISSN 0352-9045 (Let. 28, št. 3, 1998, str. 154-161)Type of material - article, component partPublish date - 1998Language - englishCOBISS.SI-ID - 1310804
Author
Raič, Dušan
Topics
mikroelektronika |
integrirana vezja |
snovanje integriranih vezij |
utežene moči |
merjenje moči |
CMOS digitalna integrirana vezja |
CMOS držalna vezja |
snovanje za male moči |
optimiranje vezij |
vrednotenje zmogljivosti |
PDP produkt odloga moči |
EDP produkt odloga energije |
prevesna vezja |
Hspice simulatorji |
metrika energije |
microelectronics |
integrated circuits |
integrated circuits design |
weighted powers |
power measuring |
CMOS digital integrated circuits |
CMOS latching circuits |
low-power design |
circuit optimization |
performance evaluation |
PDP |
power delay product |
EDP |
energy delay product |
flip-flop circuits |
Hspice simulators |
energy metrics
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Database name | Field | Year |
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Raič, Dušan | 01675 |
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