We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with ...single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm 2 chip consumes 8.5 mW from a 0.5 V supply.
Supply voltage reduction with process scaling has made the design of analog, RF and mixed mode circuits increasingly difficult. In this paper, we present the design of an ultra-low voltage, low power ...and highly integrated dual-mode receiver for 2.4-GHz ISM-band applications. The receiver operates reliably from 0.55-0.65 V and is compatible with commercial standards such as Bluetooth and ZigBee. We discuss the design challenges at low voltage supplies such as limited f T for transistors and higher nonlinearities due to limited available signal swing, and present the architectural and circuit level design techniques used to overcome these challenges. The highly integrated receiver prototype chip contains RF front-end circuits, analog baseband circuits and the RF frequency synthesizer and was fabricated in a standard digital 90-nm CMOS process; it achieves a gain of 67 dB, noise figure of 16 dB, IIP 3 of -10.5 dBm, synthesizer phase noise of - 127 dBc/Hz at 3-MHz offset, consumes 32.5 mW from 0.6 V and occupies an active area of 1.7 mm 2 .
We present an ultra-low voltage, highly linear, low noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates programmable, in-band feed-forward interferer cancellation ...at the baseband to obtain high linearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally calibrated interferer cancellation improves the IIP 3 and IIP 2 by more than 13 dB and 8 dB respectively with very little impact on the receiver noise figure. As such, it breaks the trade-off between linearity and noise figure, making it possible to use a high-gain RF front-end to achieve low noise figure without affecting the linearity of the ultra-low voltage baseband circuits. The 0.6-V 900-MHz direct-conversion receiver prototype integrates a differential LNA, RF transconductors, linear quadrature current driven passive mixers, feed-forward interferer cancellation circuits, baseband variable gain transimpedance amplifiers and second-order channel-select filters. It has a nominal conversion gain of 56.4 dB, noise figure of 5 dB, IIP 3 of -9.8 dBm and IIP 2 of 21.4 dBm. The receiver operates reliably from 0.55-0.65 V, consumes 26.4 mW and occupies an active area of 1.7 mm 2 in a 65-nm low-power CMOS process, of which the feed-forward interferer cancellation circuits consume 11.4 mW and occupies 0.43 mm 2 .
An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes ...integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.
This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation ...scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment <inline-formula> <tex-math notation="LaTeX">\pi </tex-math></inline-formula>-coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm 2 .
This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog ...converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fs rms with nominal output swing of <inline-formula> <tex-math notation="LaTeX">1.0~V_{\mathrm {ppd}} </tex-math></inline-formula> at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors' knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date.
A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that ...incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.
In this thesis, we explore the design and implementation of integrated receivers for wireless communications operating from ultra low voltage (ULV) supplies from 0.5 to 0.6V. We address the design ...challenges in receivers both for wireless personal area networks (WPAN) as well as for wide-area cellular networks. We present three receiver prototypes—(i) a 2.4GHz sliding-IF receiver operating from 0.5V, (ii) a highly integrated 2.4GHz dual-mode, zero/low-IF receiver operating from 0.6V and (iii) a 900MHz zero-IF receiver with in-band feed-forward interference cancellation operating from 0.6V. The sliding-IF receiver and dual-mode receiver are targeted for WPAN applications; and the direct conversion receiver with in-band feed-forward interference cancellation is targeted for cellular communications. The first receiver uses a sliding-IF topology and extensively relies on RF and IF passive components like on-chip inductors to achieve its low voltage operation. It further contains a 5th order Chebyshev leap-frog low-pass baseband filter on-chip to provide final channel filtering. The 0.5V sliding-IF receiver prototype in a standard 90nm CMOS technology achieves a conversion gain of 31dB, NF of 18dB and IIP3 of −22dBm, with a power consumption of 8.5mW and occupies 3.4mm2. Whereas this receiver achieved a benchmark performance in terms of low voltage operation, its FoM was lower than comparable receivers operating from higher supply voltages. The dual-mode, zero/low-IF receiver uses current-domain signal processing in the RF mixers and introduces a baseband architecture that merges the variable gain and filtering function using biquads; both techniques were demonstrated to significantly improve linearity performance for ultra low supply voltage operation. This receiver achieves a conversion gain of 67dB, NF of 16dB and IIP3 of −10.5dBm which is compatible with a commercial WPAN standard like Bluetooth or Zigbee. The receiver prototype also has an on-chip frequency synthesizer, consumes 32.5mW and occupies an area of 2.9mm 2 in 90nm CMOS. Its area is significantly smaller than the sliding-IF receiver, given the higher level of functional integration, and it achieves a 10-fold improvement in FoM. The performance of both designs remains limited by a fundamental trade-off between NF and linearity that degrades when supply voltage and available signal swings reduce. In the third ULV receiver, a novel feed-forward interference cancellation architecture is demonstrated that cancels the interferers in the current-domain baseband output of the RF mixers before they are converted in voltage signals and impose linearity and gain limitations; the proposed solution offers a significant improvement over earlier cancellation solutions especially for ultra low voltage operation and breaks the fundamental performance trade-off present in earlier designs. The 900MHz receiver operates from 0.6V, achieves a conversion gain of 55.2dB, a NF of 6.2dB and an IIP3 of −8.6dBm, consumes 26.4mW and occupies 2.56mm2 in a 65nm CMOS process. This combination of low noise, high linearity and low power meets the requirements of a commercial cellular standard like GSM. Its FoM is 10-fold better than the dual-mode receiver and is on par with the best published receivers operating from higher supply voltages. The architectural and circuit design techniques demonstrated in this thesis enables the realization of high performance wireless receivers in future CMOS processes. (Abstract shortened by UMI.)
