In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics ...are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain (A V ), cutoff frequency (f T ), and maximum oscillation frequency (f MAX ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed.
In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped ...metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations.
In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET ...using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters.
In this article, we investigate Schottky diodes with pure W and W-C alloy metal electrodes. The electrical characteristics of samples were analyzed by comparing the current density-voltage ...(<inline-formula> <tex-math notation="LaTeX">{J} - {V} </tex-math></inline-formula>) and capacitance-voltage (<inline-formula> <tex-math notation="LaTeX">{C} - {V} </tex-math></inline-formula>) curves at different annealing temperatures from 400 °C to 900 °C. The ideality factor of W-C alloy diodes annealed at 400 °C was 1.162. When W-C alloy diodes were annealed at 500 °C-900 °C, the range of <inline-formula> <tex-math notation="LaTeX">\emptyset _{B}^{I-{V}} </tex-math></inline-formula> was merely 0.08 eV, the ideality factors were below 1.15, and the difference between <inline-formula> <tex-math notation="LaTeX">\emptyset _{B}^{I-{V}} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\emptyset _{B}^{C-{V}} </tex-math></inline-formula> was smaller compared to the pure W diodes. For W-C alloy diodes annealed at 500 °C, the barrier height fluctuated only slightly, and the leakage current was suppressed effectively as the operating temperature increased. These results show that the new structure has better electrical characteristics and thermal stability. Meanwhile, transmission electron microscope (TEM) and energy-dispersive X-ray (EDX) images also verify that W-C alloy diodes reduce the interface reaction between the metal and silicon carbide (SiC), which improves the barrier inhomogeneity of W-based Schottky diodes effectively.
Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space ...which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance (<inline-formula> <tex-math notation="LaTeX">{R}_{\text {on, sp}} </tex-math></inline-formula>) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>. However, the maximum temperature of the improved VDMOSFET is 2150 K when <inline-formula> <tex-math notation="LaTeX">{V}_{\mathrm {DS}} </tex-math></inline-formula> = 950 V.
This article proposes an RC -IGBT structure with N-Si/n-Ge heterojunction (NNH-IGBT) to suppress snapback effect. Because the proposed N-Si/n-Ge heterojunction acts as a gradually reverse bias diode ...to suppress the electron flow into the N-short region, so the snapback effect can be suppressed. For the same <inline-formula> <tex-math notation="LaTeX">{\mathrm{\scriptstyle {ON}}} </tex-math></inline-formula>-state voltage drop (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {CE}} </tex-math></inline-formula>), the turn-off loss (<inline-formula> <tex-math notation="LaTeX">{E}_{\mathrm{\scriptstyle {OFF}}} </tex-math></inline-formula>) of the NNH-IGBT is lower than the conventional RC -IGBT (Con- RC -IGBT). In addition, the reverse recovery speed of NNH-IGBT is nearly identical to the Con- RC -IGBT. Because of the use of heterojunction, the NNH-IGBT is suitable for operate to suppress the snapback effect, especially at low temperatures.
This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power ...metal-oxide-semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion's strike position to SEB is proved to be the edge of the P + /P − JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure's 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one.
In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N + ...island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N + island region introduced in the second buffer can effectively reduce the impact ionization located at the N − drift/N + buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N + island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N + island buffer with a different dopant concentration of N-buffer 2 and a size of N + island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure.
This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction ...(SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS (C-VDMOS), which indicated a severe degeneration threshold of 500 V. The SiC common SJ VDMOS (C-SJ VDMOS) was proven to be sensitive to high-energy heavy-ion and represents comparative SEB performance compared with the SiC C-VDMOS. The robustness of the SiC SJ VDMOS with different single buffer layer (SBL) designs against a heavy-ion was simulated. It is found that the maximum temperature in the source metal/SiC interface and bottom of the structure could be compromised by the thickness of the buffer layer. As a result, the SiC SJ VDMOS with an optimal SBL exhibited a severe degeneration threshold of 800 V, which was a 60% increase compared to the SiC C-SJ VDMOS.
In this article, a novel snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P+ pillars at the collector side (PPC) is proposed and investigated by TCAD simulations. ...This structure features the P+ pillar structure at the side of collector and exits a gap of N-buffers above N+ collector. The P+ pillars increase the distributed resistance below the buffer layer during turn-on transient, show bipolar mode, and eliminate the snapback phenomenon. Accordingly, the structure eliminates the snapback phenomenon with a smaller half-cell pitch of Formula Omitted, making that the device is more reliable and suitable for parallel connection. For the same forward voltage drop, the turn-off loss of the PPC structure is reduced by 34%.
