A methodology for designing ternary circuits is proposed and evaluated. The method is based on a schema that consists of voltage levels, conditional blocks and weighting elements. The main idea is ...selecting appropriate voltage levels in conditional blocks and weighting them to generate desired output. In fact, the diagram is a framework for designing ternary logic gates. Hence, the optimum design can be accomplished by choosing the proper strategy particularly in conditional blocks. This could lead to minimum count of elements and decrement in complexity of the circuit. To examine the efficiency of the proposed method, three designs for standard ternary inverter (STI), ternary NAND (TNAND) and ternary NOR (TNOR) gates in carbon nanotube field-effect-transistor (CNFET) technology are presented, respectively. Several simulations are done using Synopsys HSPICE tool in 32 nm CNFET technology to measure the performance parameters for proposed designs and state-of-the-art CNFET-based designs. Moreover, the robustness of STIs in different operational conditions such as variations frequency and output load, and their senility to process deviations are measured. The simulation is done for TNAND, TNOR and half adder cell as well. The results demonstrate the proper functionality of the proposed methodology. Moreover, the designed circuits benefit from the minimum count of CNFETs, least maximum equivalent input capacitor, minimum variety of CNT diameters and delay time, while its pdp is very close to best results in comparison with state-of-the-art designs.
This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the ...unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.
A new hardware-friendly mathematical method for realizing low-complexity universal Adder cells as well as its efficient hardware implementations is proposed in this paper. This method can be used in ...binary logic, Multiple-Valued Logic (MVL) and specifically digital fuzzy systems. The proposed mathematical method can be implemented in both voltage and current modes. The voltage-mode hardware implementation is very simple and is based on input capacitors and MVL or analog inverters and buffers. In addition, the current-mode hardware implementation leads to simple and efficient structures for digital fuzzy systems. Simulations are carried out for ternary logic as well as for digital fuzzy logic with high precision by using 180
nm standard CMOS technology and at 1.8
V supply voltage. Simulation results demonstrate that the proposed designs have excellent functionality and are very suitable for implementing MVL and fuzzy arithmetic circuits.
► The proposed arithmetic method leads to efficient adders for MVL and digital fuzzy systems. ► This method is hardware-friendly. ► This method is capable of being implemented efficiently in both voltage and current modes. ► The number of inputs is arbitrary and can increase up to
r+1 for a radix-
r adder.
In this paper, a new method for designing quaternary circuits in carbon nanotube field-effect transistor (CNFET) technology is proposed. Beyond many advantages of multi-valued logics (MVLs), the ...conversion of bits of a byte between quaternary and binary logic is easy and can be done independently. Therefore, this logic can be used effectively for wholly quaternary circuit design or beside binary logic as part of a great digital system. Thanks to particular capabilities of CNFET technology, proposed designs are implemented in this technology. These complementary symmetric gates are merely made by transistors and require only one supply voltage in addition to ground level. The proposed design for implementing standard quaternary inverter (SQI) generates three inherently binary inverters in quaternary logic as well: positive quaternary inverter (PQI), negative quaternary inverter (NQI) and symmetric quaternary inverter (SyQI). Based on the proposed design, new quaternary NAND (QNAND) and quaternary NOR (QNOR) gates are presented as well. These gates could be used as fundamental blocks for implementing complex digital circuits. QNAND and QNOR may be designed to adopt up to four inputs; however, in general applications, designs with two inputs are used. Proposed gates are simulated by means of Synopsys HSPICE tool with the standard 32 nm CNFET Stanford model, and performance parameters including maximum delay time, average power and energy consumption are extracted and compared with the simulation results of the state-of-the-art designs. The results indicate priority of proposed designs such that the delay time and energy consumption are roughly equal or less than half and one-third of other presented designs, respectively. Moreover, the voltage transfer curve (VTC) of proposed gates demonstrates the proper noise margin values from 90 mV up to 113 mV for different gates. For evaluating stability and robustness of these gates, more simulations are carried out by considering process deviations in which the proposed designs demonstrate proper performance among all in the most simulations.
In this paper a design for Standard Quaternary Inverter (SQI) in Carbon Nanotube Field-Effect-Transistor (CNFET) technology is proposed. The proposed design is evaluated and compared with well-known ...designs. Therefore, several figures of merit (FOM) including maximum delay time, power consumption, Power-Delay-Product (PDP), count of utilized CNFETs and area occupation have been derived. Based on the simulation results in HSpice with standard 32 nm CNFET Stanford model, the proposed SQI is superior in terms of power consumption and PDP over other designs by roughly 50% and 150%, respectively. Furthermore, the noise margin is 19% higher than best values of other designs. For evaluating the robustness and capability, the PVT analysis and simulation of driving power and frequency-based performance of the designs were conducted. Based on the proposed SQI, the Quaternary NAND (QNAND), Quaternary NOR (QNOR) gates, Half Adder (HA) and Multiplier cells have been designed, simulated and evaluated as well. The results depict appropriate performance of designs.
