Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology ...functions as a V T -control gate. Both zero- V GS -load and diode-load logic are investigated. The noise margin of zero- V GS -load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ~0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- V GS -load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.
Data rates of plastic transponder chips have been limited to a few kHz, limited by the inherent low mobility of organic semiconductors. However, a target application for plastic RFID tags is ...Electronic Product Coding (EPC), which will require, at a base carrier frequency
f
c
=
13.56
MHz, a data rate of
f
c/512
=
52.969
kb/s. In this work, we show that the compatibility of organic semiconductors with high-k gate dielectrics allows boosting the current drive of transistors in functional circuits to EPC compatible clock rates. We demonstrate an 8
bit RFID transponder chip with critical dimension of 2
μm having a data rate of 50
kb/s at
V
DD
=
18
V.
In this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor ...channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity.
The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic ...thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent to OTFT technology, these statistical variations are also taken into account. Finally, a circuit yield analysis is presented.
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