We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 ...is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio of >106, and an electron mobility of ∼33 cm2/V·s. Uniquely, the mobility does not degrade at high gate voltages, presenting an important advantage over conventional Si transistors where enhanced surface roughness scattering severely reduces carrier mobilities at high gate-fields. A WSe2–MoS2 diode with graphene contacts is also demonstrated. The diode exhibits excellent rectification behavior and a low reverse bias current, suggesting high quality interfaces between the stacked layers. In this work, all interfaces are based on van der Waals bonding, presenting a unique device architecture where crystalline, layered materials with atomically uniform thicknesses are stacked on demand, without the lattice parameter constraints. The results demonstrate the promise of using an all-layered material system for future electronic applications.
We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we ...propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation (~±3%) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.
We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on ...the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.
We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length L g = 100 ...nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO 3 ) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau-Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective S-shaped ferroelectric charge-voltage characteristics that provides important insights into the device operation.
We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO 2 high-κ spacer and compare it with its counterpart having SiO 2 low-κ spacer. The HfO 2 spacer structure reduces series ...resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO 2 spacer device by about 3× when biased in the saturation region, and about 1.6× and 2×, respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO 2 spacer.
We fabricate n-channel silicon bulk FinFET with silicon nitride (Si 3 N 4 ) high-κ, silicon nitride/silicon dioxide dual-κ, and silicon dioxide (SiO 2 ) low-κ spacers, and compare their performance ...using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low-κ spacer FinFET is better due to lower parasitic capacitance (C par ). We show that C par in SiO 2 spacer FinFET is about half of that with Si 3 N 4 spacer. When the gate length is scaled, the contribution of C par compared with the intrinsic capacitance (C ox ) increases. For FinFET with Si 3 N 4 spacers, C par /C ox increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO 2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO 2 spacer FinFET, inverter delay is about 13% and 25% lower than Si 3 N 4 spacer FinFET for gate lengths of 30 and 10 nm, respectively.
We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf 0.8 Zr 0.2 O 2 (HZO) fabricated using a self-aligned gate last process. The FETs are ...fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 10 6 , a read endurance of > 10 10 read cycles, and a program/erase endurance of 10 7 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.
Relying on the pilot's flight experience to plan a temporary helicopter takeoff/landing site location, dispatch routes, and spraying routes often results in very long dispatch routes, imprecise ...forest area coverage, and a high extra coverage rate. An intelligent fusion algorithm was proposed to address these problems. A vector modeling method (VMM) was proposed to determine the optimum spraying route with the minimum number of turnarounds and the lower extra coverage rate. An improved genetic algorithm (IGA) was used to plan the dispatch route. Subsequently, the improved SSA (ISSA) was utilized to plan the takeoff/landing site location. An artificial neural network (ANN)-based classifier was constructed to constrain the search domain of the ISSA to avoid ponds, lakes, and other areas unsuitable for takeoff/landing. The proposed intelligent fusion algorithm is called VMM-ISSA-IGA-ANN. The planning of the takeoff/landing site locations, dispatch routes, and spraying routes for helicopter plant protection operations was carried out in four forested environments in Zhengzhou, Kaifeng, Mingguang, and Jurong, China. The planning scheme was compared with that of an aviation company. The results showed that the takeoff/landing site location derived from the VMM-ISSA-IGA-ANN was more reasonable than that obtained by the aviation company. The dispatch route was shortened by 6.51%, 23.7%, 42.07%, and 49.80%, the spraying route was shortened by 1.94%, 0.22%, 0.05%, and 0.91%, the extra coverage rate was reduced by 29.15%, 24.92%, 14.46%, and 26.04%, and the number of turnarounds was reduced by 7, 2, 21, and 22 for the four locations, respectively. This study provides a theoretical basis for route planning of helicopter aerial spraying operations and a technical reference for smart forestry applications.
•It is possible to use an intelligent fusion algorithm to plan takeoff/landing site location, dispatch route, and spraying route for a pesticide spraying helicopter.•The planning scheme obtained by the intelligent fusion algorithm is more reasonable than that planned by an aviation company.•Vector modeling method can be used to evaluate the extra rate and the number of U-turns where the spraying route cover the forest at any Angle.•By planning takeoff/landing site’s location, the length of dispatch routes can be further reduced, resulting in a reduction of operation costs.
In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device ...electrostatics and Landau-Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters.
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