In the modern era, advances in CMOS technology have increased the number of transistors and the complexity of computations that can be performed on each chip. Due to the many limitations of this ...technology, to reduce the size of the chips to the nanotechnology level and to continue Moore’s law, the unique properties of quantum cellular automata have made it a candidate for future integrated circuits. Operational units such as logic and arithmetic units are the main components of processors, among which the operation of addition and subtraction is the most widely used arithmetic operator, and the design of redundant ternary adder without publishing the carry affects the performance of processors. The main aim of this paper is to design a redundant full adder and full subtractor by employing a carry and borrow bit generator module based on ternary QCA (TQCA) innovation. Based on this, the block diagram structure of the ternary redundant adder/subtractor-based TQCA circuit is presented, which includes a proposed new carry/borrow generator gate based on TQCA. The proposed full adder design has 423 ternary cells, area 0.09 µm
2
and cost 647.19, and the full subtractor has 431 ternary cells, area 0.09 µm
2
and cost 710.7. For validation, the circuits were simulated with the TQCAsim software. The results of this innovation show that the proposed architecture has significant advantages.
Today, with the continuation of the reduction of the dimensions of transistors, the thickness of the gate is so small that it causes the leakage currents of the transistors to be very high. This ...prevents the reduction of power consumption and the speed of transistors. Also, construction costs, especially the lithography process, have increased greatly. In the next decade or two, as this trend continues, transistors will be the same size as atoms, and the laws of quantum physics will explain the behavior of atoms and no longer apply classical laws. Quantum-dot cellular automata technology is the vision of a new path for advancement in nanoelectronics and the design of small-scale computational circuits. Ternary logic is a promising proposition for designing QCA-based logic circuits. In this paper, for the first time, Two proposed single-trit comparator circuits based on ternary quantum cellular automaton technology were introduced. The first circuit was designed using a diagram block structure and truth table with 140 cells and area
0.108
μ
m
2
. Using a physical proof of energy between cells, the second proposed circuit with 24 cells and area
0.011
μ
m
2
was designed. To measure the accuracy of performance, the circuit was simulated in TQCAsim software. Quantum cells have superiority with the aim of reducing power consumption, occupied space, and dramatically increasing work frequency. Comparisons show that the designs presented have improved compared to the previous ones.
In this paper, photonic crystal structures are proposed to design configurable all-optical logic gates. These structures offer XOR/AND and XNOR/NAND logic operations which provide two logic functions ...in an output port by means of a control signal that provides more flexibility in circuit design procedure. Also, the proposed structures offer a half adder (AND/XOR) and its inverted logic (NAND/ XNOR). The proposed structures include a nonlinear directional coupler and Y-junctions. In the proposed structures, the nonlinear directional coupler, which consists of nonlinear rods made of silicon nano-crystals, is used to provide a phase shifter for different input powers. Finite difference time domain and plane wave expansion methods are used to evaluate the proposed structures. Effects of variations in wavelength, refractive index and radius of rods on the performance of the proposed structures are studied which indicate the robustness of the proposed structures against process variation. Simulation results show that the switching power and bit rateof the proposed structures are 3 W and 1 Tbits/s respectively.
Distributed quantum system is a well-known method to overcome the problems of designing and manufacturing large quantum systems to achieve higher processing power in the world of quantum processing. ...In distributed quantum computing, a number of limited-capacity quantum circuits communicating with each other through communication channels operate as a large quantum circuit. The most essential step in designing a distributed quantum system is to optimize the communication between the components to reduce the overhead cost of communications. In this study, based on the commuting of quantum gates, an efficient method is proposed to reduce the number of teleportations required to perform distributed quantum circuits (DQCs). The results obtained from the evaluation of our method on benchmark circuits indicate an impressive decrease in the number of teleportations and a significant reduction in the execution time compared to the present methods.
Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow ...zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.
This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors ...(CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4 × 4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.
In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the ...new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.
Reversible logic is considered as a basic requirement for designing quantum computers. Reversible circuits do not waste energy. The use of this logic in low-power complementary ...metal–oxide–semiconductor circuits, quantum computing, and DNA computing has rendered reversible logic integral in today’s technology. Multiplication is regarded as a major operation in the arithmetic. Herein, four optimized parity-preserving reversible signed and unsigned multiplier circuits are presented to reduce the QUANTUM COST of the circuits. The designs can be expanded to an
N
×
N
dimension. We prove that these multiplier circuits have lower QUANTUM COST, CONSTANT INPUTs, and GARBAGE OUTPUTs compared with previous studies.
Nanotechnologies, notably quantum-dot cellular automata, have achieved major attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, ...particularly owning to its considerable reduction in size, high switching speed and ultra-low energy consumption, is considered as a potential alternative for the CMOS technology. As the memory unit is one of the most essential components in a digital system, designing a well-optimized QCA random access memory (RAM) cell is an important area of research. In this paper, a new five-input majority gate is presented which is suitable for implementing efficient single-layer QCA circuits. In addition, a new RAM cell with set and reset capabilities is designed based on the proposed majority gate, which has an efficient and low-energy structure. The functionality, performance and energy consumption of the proposed designs are evaluated based on the QCADesigner and QCAPro tools. According to the simulation results, the proposed RAM design leads to on average 38% lower total energy dissipation, 25% smaller area, 20% lower cell count, 28% lower delay and 60% lower QCA cost as compared to its previous counterparts.
Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more ...prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied.
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