This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction ...and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper.
This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of ...the VCO by the power amplifier. Timing errors between the quadrature phases used in the phase-rotating divider introduce fractional spurs at the output. In this design, the timing errors are measured with a stochastic time-to-digital converter with 20 fs resolution, and corrected to suppress output spurs. The fractional divider has been implemented in a 45 nm CMOS LP process and its core dissipates an estimated 17 mA current from a 1.1 V supply. After calibration, fractional spurs are on average below -59 dBc and -50 dBc (¿ ~ 2 dB over 10 samples) with a 2.5 and 3.8 GHz output frequency respectively. Calibration performance has been confirmed for temperatures from -20°C up to 85°C. The low spur level facilitates radio co-existence with no need for additional filtering. This makes this divider a good candidate for WiFi and WiMAX radios up to 3.8 GHz.
The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply ...sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.
Phase noise in digital frequency dividers Levantino, S.; Romano, L.; Pellerano, S. ...
IEEE journal of solid-state circuits,
05/2004, Volume:
39, Issue:
5
Journal Article
Peer reviewed
This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 ...dual-modulus prescalers integrated in a 0.35-/spl mu/m CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is -163 dBc/Hz referred to the 78-MHz output.
This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to ...introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8
A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based ...phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.
An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes ...integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.
Forty patients with skin diseases of various origins were treated with a combination of three creams, the respective bases of which were clobetasone butyrate, sodium fusidate and ketoconazole. ...Satisfactory results were obtained in 97.5% of cases, with remission of symptoms and good healing of lesions. Tolerance was excellent in 97.5% of cases, with only one patient complaining of burning sensations after the applications.
Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2times2 ...MIMO WLAN transceiver RFIC implemented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of -63 dBm while receiving 108Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of AWGN noise is -76 dBm. Linearized 3.3-V 5-GHz power amplifiers with P 1dB =20.5 \ dBm deliver an average power of +13/+16 dBm each, in MIMO/SISO modes respectively (EVM=-27/-25 dB). The measured performance demonstrates the effectiveness of the isolation techniques employed. The system in a package includes an 18 mm 2 die and microstrip front-end matching networks implemented on a flip-chip package
