Real-time multimedia applications are increasingly achieving success in the everyday world. Thereby, multimedia information relies on security to protect private life. The Advanced Encryption ...Standard (AES) has been designed to secure different applications. Yet, some limitations are given, making it inappropriate for secure video storation and transmission. The limitations are the time complexity, the multiple iterations, and the predefined substitution box. Thus, any user can use it to break the encryption. Moreover, the multiple iterations augment the need for CPU usage, and so the overall run time. Hence, it is necessary to modify the AES algorithm to make it more appropriate for securing video frames transmission over insecure channel. In this paper, an Improved AES (IAES) is put forward, which improves both diffusion and confusion in ciphered video. Our work consists in the following two main points: First, we propose to eliminate both shift-row and sub-byte transformations and replace them with a mix-row operation. This task reduces the run time, which presents a significant factor for real-time video transmission. Equally important, we propose to use the henon chaotic map in the key generation procedure, which provides more randomness. The Hash Algorithm SHA-3 is used to generate the initial conditions of the chaotic attractor. The video encryption procedure is verified with success, and the experimental results confirm that the novel algorithm combining chaos and IAES augments the entropy of the ciphered video by 15% and reduces the complexity time for both encryption and decryption compared to the standard one. Security analysis is successfully performed, and the results prove that our suggested technique provides the basics of cryptography with more correctness. The PRNG is tested by NIST 800–22 test suit, which indicates that it is suitable for secure image encryption. It provides a large key space of 2
128
which resists the brute-force attack. All in all, the findings confirm that the novel security approach eliminates the limitation of the existing AES and provides a trade-off between speed and safety levels to secure video transmission.
Due to rapid development in secured technological devices, the efficient implementation of a large field-size elliptic curve cryptosystem (ECC) is becoming demanding in many critical applications. ...Therefore, this paper presents a new Montgomery point multiplication (PM) algorithm to optimize and balance the signal flow and resource utilization efficiency. Thereafter, we have presented an efficient ECC processor architecture over <inline-formula> <tex-math notation="LaTeX">GF(2^{m}) </tex-math></inline-formula> with m = 409 and 571 for the proposed Montgomery PM algorithm. Finally, we have given a detailed comparison and performance analysis (in terms of area-delay product) to show that the proposed cryptographic processor has superior performance as compared to the competing designs. The implementation results after place & route on Xilinx Virtex 7 and Kintex Ultrascale+ are provided. The achieved results reveal that the proposed large field-size ECC processor (and the proposed design strategy) can be extended and applied in many security-demanding applications.
The Elliptic Curve Digital Signature Algorithm(ECDSA) is the analog to the Digital Signature Algorithm(DSA). Based on the elliptic curve, which uses a small key compared to the others public-key ...algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curveswith the 163-bit key length recommended by the NIST (National Institute of Standards and Technology). It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip) and Random Number Generator IP (RNG IP). Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW). Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks.
Systolic finite field multiplier over <inline-formula> <tex-math notation="LaTeX">GF(2^{m}) </tex-math></inline-formula>, because of its superior features such as high throughput and regularity, is ...highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field <inline-formula> <tex-math notation="LaTeX">(GF(2^{m})) </tex-math></inline-formula> is proposed. Novel Toeplitz matrix-vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.
With the rapid evolution of security technology, small field-size elliptic curve-based point multiplication (PM) has gradually become obsolete, leading to the implementation of PM with large field ...sizes. From this perspective, in this article, through a novel algorithm-architecture co-design strategy, we propose an efficient implementation of the PM on the elliptic curve over GF(2<inline-formula> <tex-math notation="LaTeX">^m)</tex-math> </inline-formula> (particularly targeting large field sizes). To achieve an area-time-efficient elliptic curve cryptography (ECC) processor implementation on the field-programmable gate array (FPGA) platform, we have proposed a bottom-up approach based on three coherent interdependent layers of efforts. First, we proposed an efficient digit-serial versatile multiplier (DSVM) based on polynomial representation. The system is built using the four-way overlap-free Karatsuba algorithm (OFKA) and a modified radix-n interleaved multiplication (mRnIM) technique (for area and time complexities reduction). Of course, the efficiency of the proposed multiplier is demonstrated by the complexity analysis and comparison with the existing reported designs. Second, we have adopted the López-Dahab (LD) Montgomery PM algorithm to avoid data dependency and enhance signal control in the ECC design. Meanwhile, a series of resource optimization techniques have also been adopted for the proposed ECC processor to optimize the overall design efficiency further. Third, the proposed ECC PM architecture is then implemented on the FPGA platform, showing that the proposed ECC crypto-processor obtains the least area-delay product (ADP) among all the existing structures for the large field sizes.
•Development of a new 2D-FRS code.•Gaussian approximation is used to analyze performance analysis of 2D-FRS system.•Simulation validation of 2D-FRS numerical model.•Power saving feature at 2D-FRS ...receiver.•Accommodation of large number of active users with high bit rate.
In this paper a new algorithm to generate two dimensional fixed right shifting (2D-FRS) code sequences is proposed, which is based on spectral/spatial incoherent OCDMA system. The proposed 2D-FRS algorithm is designed using 1D-FRS code with minimum cross correlation (MCC). The 2D-FRS codes enhance the system cardinality and offer elimination capability of MCC and its associated phase induced intensity noise (PIIN). Furthermore, the proposed algorithm allows multiple users with different code sequences to transmit data with minimum likelihood of interference. The architecture of transmitter-receiver structure of spectral/spatial 2D-FRS OCDMA system is presented. Gaussian approximation is used to analyze performance of the proposed 2D-FRS OCDMA system by investigating noise sources at photodiodes (PDs). It is shown that PD-1 and PD-3 have lower contribution in terms of noise power as compared to PD-0 and PD-2 due to division operation in MCC elimination process at the balanced detectors. Simulation results also validates the proposed system for an agreeable bit error rate (BER) of 10−9. It is observed that the 2-D FRS OCDMA system can support a higher number of users in deterministic and stochastic methods compared to the reported techniques such as Diagonal Eigenvalue Unity (DEU) and Two-Dimensional Diluted Perfect Difference codes (2D-DPD codes). The 2D-FRS cardinality surpassing the 2D-DPD and 2D-DEU by ≈71.21% and ≈9.09% respectively at the BER of 10−9. At 622 Mbits/s transmission data rate, the 2-D FRS meets the optical transmission requirements with lowest effective transmitted source power (Psr), −27.5 dBm in comparison to published codes.
The advent of the Internet of Things (IoT) has enabled millions of potential new uses for consumers and businesses. However, with these new uses emerge some of the more pronounced risks in the ...connected object domain. Finite fields play a crucial role in many public-key cryptographic algorithms (PKCs), which are used extensively for the security and privacy of IoT devices, consumer electronic equipment, and software systems. Given that inversion is the most sensitive and costly finite field arithmetic operation in PKCs, this paper proposes a new, fast, constant-time inverter over prime fields Fp based on the traditional Binary Extended Euclidean (BEE) algorithm. A modified BEE algorithm (MBEEA) resistant to simple power analysis attacks (SPA) is presented, and the design performance area-delay over Fp is explored. Furthermore, the BEE algorithm, modular addition, and subtraction are revisited to optimize and balance the MBEEA signal flow and resource utilization efficiency. The proposed MBEEA architecture was implemented and tested on Xilinx FPGA Virtex #5, #6, and #7 devices. Our implementation over Fp (length of
= 256 bits) with 2035 slices achieved one modular inversion in only 1.12 μs on Virtex-7. Finally, we conducted a thorough comparison and performance analysis to demonstrate that the proposed design outperforms the competing designs, i.e., has a lower area-delay product (ADP) than the reported inverters.
The advent of the Internet of Things (IoT) has enabled millions of potential new uses for consumers and businesses. However, with these new uses emerge some of the more pronounced risks in the ...connected object domain. Finite fields play a crucial role in many public-key cryptographic algorithms (PKCs), which are used extensively for the security and privacy of IoT devices, consumer electronic equipment, and software systems. Given that inversion is the most sensitive and costly finite field arithmetic operation in PKCs, this paper proposes a new, fast, constant-time inverter over prime fields Fsub.p based on the traditional Binary Extended Euclidean (BEE) algorithm. A modified BEE algorithm (MBEEA) resistant to simple power analysis attacks (SPA) is presented, and the design performance area-delay over Fsub.p is explored. Furthermore, the BEE algorithm, modular addition, and subtraction are revisited to optimize and balance the MBEEA signal flow and resource utilization efficiency. The proposed MBEEA architecture was implemented and tested on Xilinx FPGA Virtex #5, #6, and #7 devices. Our implementation over Fsub.p (length of p = 256 bits) with 2035 slices achieved one modular inversion in only 1.12 μs on Virtex-7. Finally, we conducted a thorough comparison and performance analysis to demonstrate that the proposed design outperforms the competing designs, i.e., has a lower area-delay product (ADP) than the reported inverters.
The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a ...compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs’ (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices.
The advent of the Internet of Things (IoT) has enabled millions of potential new uses for consumers and businesses. However, with these new uses emerge some of the more pronounced risks in the ...connected object domain. Finite fields play a crucial role in many public-key cryptographic algorithms (PKCs), which are used extensively for the security and privacy of IoT devices, consumer electronic equipment, and software systems. Given that inversion is the most sensitive and costly finite field arithmetic operation in PKCs, this paper proposes a new, fast, constant-time inverter over prime fields F p based on the traditional Binary Extended Euclidean (BEE) algorithm. A modified BEE algorithm (MBEEA) resistant to simple power analysis attacks (SPA) is presented, and the design performance area-delay over F p is explored. Furthermore, the BEE algorithm, modular addition, and subtraction are revisited to optimize and balance the MBEEA signal flow and resource utilization efficiency. The proposed MBEEA architecture was implemented and tested on Xilinx FPGA Virtex #5, #6, and #7 devices. Our implementation over F p (length of p = 256 bits) with 2035 slices achieved one modular inversion in only 1.12 μs on Virtex-7. Finally, we conducted a thorough comparison and performance analysis to demonstrate that the proposed design outperforms the competing designs, i.e., has a lower area-delay product (ADP) than the reported inverters.
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