A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the ...number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.
A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and ...generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown.
Conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to netlists of RSFQ ...circuits considering reduction of the number of clocked gates including DFFs for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer which can be utilized for realizing logic-OR. The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. Detection methods of replaceable gates with those two kinds of gates are proposed. An ATPG tool is utilized for detecting replaceable OR gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU and a 64-bit ALU. Evaluation results show that the number of clocked gates and the latency in cycles of circuits are reduced about 10%. The delay time of the converted circuits has been estimated and reduction of delay overhead is discussed.
Abstract
We examine digital behavior of faults caused by a change of the order of the pulse arrivals in Rapid Single-Flux-Quantum (RSFQ) logic circuits. Based on the timing fault model, we present a ...flow of automatic test pattern generation for testing digital RSFQ chips. As the test pattern generation repeatedly executes fault simulation, the scalability depends on computational cost of the simulation. We propose an efficient fault simulation method based on two ideas. First, we share computation for the fault-free circuit and faulty circuits as much as possible. Secondly, we exploit the pipelined behavior of RSFQ logic circuits to suppress computation for unnecessary signals. We have implemented our simulation method and obtained evaluation results to show that our method is effective for large circuits.
An automated layout design flow for rapid single-flux-quantum (RSFQ) circuits is proposed. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive ...transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: 1) cell clustering, 2) cell placement and JTL routing in each cluster, and 3) cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.
We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including ...Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.
An automatic wire-routing method of passive transmission lines (PTLs) for single-flux-quantum digital circuits is proposed. The method considers the wire routing of a rectangular region between ...adjacent columns of active devices. To perform wire routing considering the difference between the timing variabilities of active devices and those of PTLs, the proposed wire-routing method provides paths of PTLs with a specified additional length for delay insertion. The problem is formulated as integer linear programming. Experimental results show that compact layouts are obtained.
A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. ...It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0-μm Nb/AlO x /Nb nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm 2 , and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm 2 . It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of 6.25 × 10 9 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any 4n-bit processing.
The problem of evaluating the matrix polynomial I+A+A2+…+AN-1 with a reduced number of matrix multiplications has long been considered. Several algorithms have been proposed for this problem, which ...find a procedure requiring O(log N) matrix multiplications for a given N. Among them, the hybrid algorithm based on the double-base representation of N, i.e., using mixed radices 2 and 3, proposed by Dimitrov and Cooklev is most efficient. It has been suggested by them that the use of higher radices would not bring any more efficient algorithms. In this paper, we show that we can derive more efficient algorithms by using higher radices, and propose several efficient algorithms.
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