This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet . The test platform consisting of a phase-leg ...configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μ s is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.
The power system planning and protection studies are becoming more challenging due to the rapid increase in penetration levels of converter-interfaced renewables. Type-IV wind turbine generators ...(WTGs) and photovoltaic panels are interfaced to the grid through a full-scale converter, and their short-circuit current contributions are mainly designated by the converter control and associated current limits. This paper proposes a new phasor domain modeling approach for the wind parks (WPs) with Type-IV WTGs, using the concept of control-based equivalent circuits. The proposed model precisely represents the detailed electromagnetic transient (EMT)-type model in steady state, and is able to account for the fault-ride-through function of the WTG control as well as its specific decoupled sequence control scheme in addition to the traditional coupled control scheme. Although the collector grid and WTGs inside the WP are represented with their aggregated models, the overall reactive power control structure of the WP is preserved by taking the central WP controller into account. The accuracy of the proposed model is validated through detailed EMT simulations.
Safety Through Switching Speed Kay, John A.; Allen, Philip; Norton, Eric
IEEE transactions on industry applications,
05/2024
Journal Article
Peer reviewed
This paper expands on the relationship between fault interrupting speed versus incident energy. It will provide some details about the world's fastest low voltage (LV) circuit breaking technology. ...With ultra-fast and consistent clearing times, devices using this technology provide the fastest method of removing fault currents. This sequentially reduces fault incident energies to nearly non-existent levels. Adding this switching technology could be the next step in enhancing your safety program. This new and very rapidly growing technology is the LV Solid-State Circuit Breaker (SSCB). Using silicon carbide (SiC) semiconductor modules, and unique current sensing methodologies, furnishes the SSCB with the ability to provide extremely rapid, consistent, and arc-less switching. Since the interruption of the current is performed without any electro-mechanical contacts, these devices can provide an almost unlimited number of switching operations. While at the same time, release virtually no arc flash incident energy whilst also limiting the let-through current to the lowest level in industry. In this work, we will provide an overview of this new technology and how Petroleum and Chemical industry users can take advantage of eliminating almost all release of arc flash incident energy associated with traditional LV molded case circuit breakers (MCCB). And, at the same time, significantly reduce the electromechanical stress on the connected load while virtually eliminating the need for breaker maintenance providing a protection device with a much higher mean time between failures.
Fault diagnosis in electronic circuits is an emerging area of research, where fully automated diagnosis systems are being developed for the investigation of the circuits. Developing test methods for ...the diagnosis of faults in analog circuits is still a complex task. Consequently, a technique for the fault diagnosis in analog circuits is designed by proposing a new optimization algorithm, named, rider optimization algorithm (ROA). The development of ROA is based on a group of riders, racing toward a target location. Moreover, a classifier, termed RideNN, is developed by including the proposed algorithm as the training algorithm for the neural network (NN). RideNN, along with the orthogonal transformation and Bhattacharyya coefficient, is applied for the fault diagnosis of analog circuits. The proposed technique is experimented using three basic circuits, such as triangular wave generator (TWG), low noise bipolar transistor amplifier (BTA), and differentiator (DIF) and an application circuit, solar power converter (SPC). The performance is evaluated using two evaluation metrics, namely, accuracy (ACC) and false alarm ratio (FAR). The analysis results show that the proposed technique attains an ACC of 99.9% in TWG, 99.9% in BTA, 99% in DIF, and 95% in SPC without noise.
Low-power receivers (RXs) with 100 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>-scale power consumption can enable several power/energy-constrained ...Internet-of-Things (IoT) applications. However, achieving sensitivity, interferer tolerance, and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula> OFF-chip components. This article presents a low-power RX that utilizes a novel distributed <inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula>-path mixer architecture to enable a sub-150-<inline-formula> <tex-math notation="LaTeX">\mu \text {W} </tex-math></inline-formula> multi-tone RX achieving wide operating range, high sensitivity and interferer tolerance. The proposed architecture is implemented in 22 nm CMOS and occupies 0.48 mm2. The RX achieves a 500-MHz operating range from 0.4 to 0.9 GHz with up to −85-dbm sensitivity for 100-kbps data rate with < 150-<inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> power consumption and up to −41-dB SIR tolerance.
Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. ...It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.
Most work in quantum circuit optimization has been performed in isolation from the results of quantum fault-tolerance. Here we present a polynomial-time algorithm for optimizing quantum circuits that ...takes the actual implementation of fault-tolerant logical gates into consideration. Our algorithm resynthesizes quantum circuits composed of Clifford group and T gates, the latter being typically the most costly gate in fault-tolerant models, e.g., those based on the Steane or surface codes, with the purpose of minimizing both T-count and T-depth. A major feature of the algorithm is the ability to resynthesize circuits with ancillae at effectively no additional cost, allowing space-time trade-offs to be easily explored. The tested benchmarks show up to 65.7% reduction in T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7% reduction in T-depth using ancillae.
This paper provides a pragmatic solution to the challenge of testing fault current interruption of high-voltage direct current (HVDC) circuit breakers (CBs). The critical parameters in the design of ...a test circuit capable of supplying the necessary stresses: current, energy, and voltage (both during and after interruption) are discussed. In addition, a practical implementation of a test circuit based on ac short-circuit generators operated at low power frequency, which is capable of testing the current interruption performance of the proposed technologies of HVDC CBs, is discussed. Tests validating the proposed method and circuit have been conducted on a prototype of an HVDC CB and the test results are presented. Since the performance of some technologies of HVDC CBs can depend on the magnitude of the interrupted current, four test duties are defined and demonstrated in the paper. Moreover, testing of HVDC CBs using ac short-circuit generators poses new challenges, such as the application of dielectric dc stress after current interruption and the protection of both the test-object as well as the test-circuit components when the HVDC CB fails to interrupt. Methods to overcome these challenges are developed and practically demonstrated in a test laboratory. Finally, taking into account the available resources of the author's test laboratory, the capability to test multiple series-connected modules of different technologies of HVDC CBs is verified and example cases are demonstrated. Six short-circuit generators (13 500 MVA @ 50 Hz) and up to ten step-up transformers (up to 550 kV) were actually used.
We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm 2 footprint for hybrid integration of a flexible probe and a 256-channel integrated ...circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 μm. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 μW from 1.2 V and 1.8 V supplies in an area of 0.0161 mm 2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 μV rms input-referred noise from 0.5 Hz to 10 kHz, and 48 MΩ input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.
The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous ...potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.
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