Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of ...nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme.
An ultra-compact monolithic microwave integrated circuit active variable phase shifter is proposed and implemented using CMOS technology. It is a reflective-type phase shifter consisting of a compact ...three-transistor active circulator and a second-order LC network. The use of an active inductor in the second-order LC network makes this phase shifter all active and ultra compact with a size of only 0.357 including bonding pads. The phase shifter was designed and demonstrated at 2.4 GHz and has a linear and continuously tunable range of 120 across the 2.4-GHz industrial-scientific-medical band.
Broadening the optical absorption of organic photovoltaic (OPV) materials by enhancing the intramolecular push-pull effect is a general and effective method to improve the power conversion ...efficiencies of OPV cells. However, in terms of the electron acceptors, the most common molecular design strategy of halogenation usually results in down-shifted molecular energy levels, thereby leading to decreased open-circuit voltages in the devices. Herein, we report a chlorinated non-fullerene acceptor, which exhibits an extended optical absorption and meanwhile displays a higher voltage than its fluorinated counterpart in the devices. This unexpected phenomenon can be ascribed to the reduced non-radiative energy loss (0.206 eV). Due to the simultaneously improved short-circuit current density and open-circuit voltage, a high efficiency of 16.5% is achieved. This study demonstrates that finely tuning the OPV materials to reduce the bandgap-voltage offset has great potential for boosting the efficiency.
Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion ...region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.
In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder ...(ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope ...for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
Recently, distributed generators and sensitive loads have been widely used. They enable a solid-state circuit breaker (SSCB), which is an imperative device to get acceptable power quality of ac power ...grid systems. The existing ac SSCB composed of a silicon-controlled rectifier requires some auxiliary mechanical devices to achieve the reclosing operation before fault recovery. However, the new ac SSCB can achieve a quick breaking operation and then be reclosed with no auxiliary mechanical devices or complex control even under sustained short-circuit fault because the commutation capacitors are charged naturally without any complex control of main thyristors and auxiliary ones. The performance features of the proposed ac SSCB are verified through the experiment results of the short-circuit faults.
Grid-connected inverters are known to become unstable when the grid impedance is high. Existing approaches to analyzing such instability are based on inverter control models that account for the grid ...impedance and the coupling with other grid-connected inverters. A new method to determine inverter-grid system stability using only the inverter output impedance and the grid impedance is developed in this paper. It will be shown that a grid-connected inverter will remain stable if the ratio between the grid impedance and the inverter output impedance satisfies the Nyquist stability criterion. This new impedance-based stability criterion is a generalization to the existing stability criterion for voltage-source systems, and can be applied to all current-source systems. A single-phase solar inverter is studied to demonstrate the application of the proposed method.
This paper presents a fully integrated transceiver chipset based on the WiGig/IEEE 802.11ad standard targeting mobile usage. The chipset is developed for single-carrier (SC) modulation, which is ...suitable for reduced power consumption. However, the SC modulation is sensitive to in-band amplitude variations, mainly made worse by the gain variations of analog circuits and multipath delay spread. In order to compensate for these gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size. The test chip achieves 1.8 Gb/s MAC throughput for up to 40 cm and 1.5 Gb/s for up to 1 m while consuming 788 mW in TX and 984 mW in RX mode.
Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing ...optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications.
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