Solid-state dc circuit breaker (SSCB) plays a very important role in the dc system protection against fast rising overload and short-circuit faults. Among various SSCB topologies, z-source dc circuit ...breakers (ZSCBs) have a great ability to interrupt the fault at a much faster rate, without even using a fault sensing circuit. However, ZSCBs suffer from various issues such as: 1) high starting current in the main thyristor (SCR), 2) unwanted power flow in the load during commissioning and reclosing of ZSCBs, and 3) negative current flow through the load at starting/reclosing of the ZSCB. These problems arise due to the fact that the z-source series capacitor stays charged even after the fault is interrupted or cleared. Unwanted power flow, negative current circulation in the load needs special attention especially in unidirectional loads and also in electromechanical systems. Hence, this article proposes a modified ZSCB to address the aforementioned problems. The proposed topology employs power semiconductor devices such as IGBTs to discharge the capacitor before the next interruption cycle. Initially, a detailed analysis, with simulation and experimental validation showing the issues with the existing ZSCB is presented. Later, a detailed analysis of the proposed modified ZSCB is presented, followed by an extensive simulation and experimental validation on a laboratory scale 120-V/3.5-A (400 W) prototype.
An accurate equivalent circuit model (ECM) for general multiwire multiorder printed circuit board (PCB) metagratings (MGs) is developed. The effective impedances of the grating wires are modeled as ...lumped loads in the ECM. The numerous propagating Floquet harmonics supported by the grating are modeled as circuit ports. Based on the desired field transformation for the MG, a set of required scattering parameters for its ECM is derived. The equivalent lumped loads are subsequently optimized to realize these parameters, which is analogous to shaping the diffraction pattern of the MG to match the desired functionality. Within this framework, it is possible to encode multiple functions into a single device by simultaneously optimizing all relevant entries of the ECM scattering matrix. Using the proposed technique, an angle-multiplexed multifunctional MG is designed and investigated.
This article proposes a novel ultra-fast self-powered bidirectional solid-state circuit breaker (SSCB) with voltage overshoot suppression that uses gallium nitride switches with very low conduction ...losses. This SSCB can be used in low and medium ac/dc networks for both short-circuit protection and overcurrent protection. An exhaustive methodology for RCD snubber design applied to SSCBs is provided. A comprehensive review of the technical literature is presented exhibiting that the proposed SSCB reduces conduction losses and detection time in comparison with other similar SSCBs. The performance features of the proposed SSCB are verified through the functional tests that are carried out employing a hardware-implemented prototype. Experimental results confirm that our proposal is able to detect and process the short-circuit failure in 282 ns; the authors have not found any faster results in the literature.
A Survey on Hybrid Circuit-Breaker Topologies Shukla, Anshuman; Demetriades, Georgios D.
IEEE transactions on power delivery,
2015-April, 2015-4-00, Volume:
30, Issue:
2
Journal Article
Peer reviewed
The applications of power semiconductors in circuit-breaker (CB) technology can help achieve considerable improvement in its performance and possible new capabilities. In this paper, new trends in ...power electronics for the applications in CBs are presented. It also summarizes and reviews the appropriate hybrid mechanical-static CB topologies. Various conventional and derived topologies for ac as well as dc applications are described. Discussions about common and future trends in this technology development are presented. This study will provide a useful framework and point of reference for the future development of hybrid CBs for various different applications.
An all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2× time amplifiers, the TDC ...efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 μm CMOS, shows the minimum resolution of 1.25 ps with a total conversion range of 2.5 ns, the maximum operating frequency of 250 MHz, and power consumption of 1.8 mW at 60 MHz. The measured rms jitter of PLL was 5.03 ps at 960 MHz.
This paper describes a project to create a novel design and simulation tool for quantum-dot cellular automata (QCA), namely QCADesigner. QCA logic and circuit designers require a rapid and accurate ...simulation and design layout tool to determine the functionality of QCA circuits. QCADesigner gives the designer the ability to quickly layout a QCA design by providing an extensive set of CAD tools. As well, several simulation engines facilitate rapid and accurate simulation. This tool has already been used to design full-adders, barrel shifters, random-access memories, etc. These verified layouts provide motivation to continue efforts toward a final implementation of QCA circuits.
This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme ...for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.
Machine Learning (ML) has shown promising results in predicting the behavior of analog circuits. However, in order to completely cover the design space for today's complicated circuits, supervised ML ...requires a large number of labeled samples which is time-consuming to provide. Furthermore, a separate dataset must be collected for each circuit topology making all other previously gathered datasets useless. In this paper, we first present a database including labeled and unlabeled data. We use neural networks to determine the behavior of complicated topologies by combining the more simple ones. By generating such unlabeled data, the time for providing the training set is significantly reduced compared to the conventional approaches. Using this database, we propose a fully-automated analog circuit generator framework, AnGeL. AnGeL performs all the schematic circuit design steps from deciding the circuit topology to determining the circuit parameters i.e. sizing. Our results show that for multiple circuit topologies, in comparison to the state-of-the-art works while maintaining the same accuracy, the required labeled data is reduced by 4.7x -1090x. Also, the runtime of AnGeL is 2.9x -75x faster.
A new common-mode bandstop filter (CM-BSF) with an all-pass performance (from dc to 9 GHz) for differential signals is proposed by using a C-shaped patterned ground structure (PGS) with meandered ...signal lines on a two-layer printed circuit board (PCB). This technique can successfully generate two close transmission zeros in common-mode within the frequencies of concern. A corresponding equivalent circuit model is established to predict the filter behaviors, and a formula for common-mode transmission zeros is derived based on the circuit model. Next, a design method is developed and a synthesis procedure is proposed. According to the procedure, a wideband CM-BSF is synthesized and fabricated on a two-layer PCB. In addition, the simulation and experiment results are demonstrated to verify the technique and show excellent performance of the proposed CM-BSF. It is shown that common-mode noise can be suppressed over 10 dB from 1.9 to 8.9 GHz with 130% fractional bandwidth (FBW) while the insertion loss of differential-mode can be kept less than 3 dB from dc to 9 GHz. The electrical size is only 0.21 λ g ×0.21 λ g , where λ g is the wavelength of the stopband central frequency. To sum up, the proposed CM-BSF has merits of low cost (two layer), a simple geometric structure, a compact size, and a large common-mode FBW. Most importantly, the filter can keep good signal integrity of the digital differential signals due to its all-pass characteristic.
A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled ...from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.
