Printed circuit board (PCB) manufacturing processes are becoming increasingly complex, where even minor defects can impair product performance and yield rates. Precisely identifying PCB defects is ...critical but remains challenging. Traditional PCB defect detection methods, such as visual inspection and automated technologies, have limitations. While defects can be readily identified based on symmetry, the operational aspect proves to be quite challenging. Deep learning has shown promise in defect detection; however, current deep learning models for PCB defect detection still face issues like large model size, slow detection speed, and suboptimal accuracy. This paper proposes a lightweight YOLOv8 (You Only Look Once version 8)-based model called LW-YOLO (Lightweight You Only Look Once) to address these limitations. Specifically, LW-YOLO incorporates a bidirectional feature pyramid network for multiscale feature fusion, a Partial Convolution module to reduce redundant calculations, and a Minimum Point Distance Intersection over Union loss function to simplify optimization and improve accuracy. Based on the experimental data, LW-YOLO achieved an mAP0.5 of 96.4%, which is 2.2 percentage points higher than YOLOv8; the precision reached 97.1%, surpassing YOLOv8 by 1.7 percentage points; and at the same time, LW-YOLO achieved an FPS of 141.5. The proposed strategies effectively enhance efficiency and accuracy for deep-learning-based PCB defect detection.
This paper proposes an adaptive protection scheme for distribution systems with distributed generations (DGs). To mitigate the influences on the protection devices by DGs, an online calculation ...method of fault current under various system operation conditions is presented. By sampling local available measurements in the buses, a proposed optimized estimation method is used to calculate the Thevenin equivalent circuit parameters of the system dynamically. Moreover, the short-circuit current can be calculated accurately to set the overcurrent relay protection value considering the behavior of DGs during the fault. To ensure the accurate operation of the protection devices, a coordinated protection scheme, including primary and backup protection is presented. Performances of the proposed method and scheme have been verified by simulations on a sample distribution system based on PSCAD/EMTDC. The sensitivity and selectivity of the coordination between primary and backup protection are satisfied under different system operation conditions, fault locations, and types.
This paper presents a systematic approach for the statistical simulation of nonlinear networks with uncertain circuit elements. The proposed technique is based on spectral expansions of the elements' ...constitutive equations (I-V characteristics) into polynomial chaos series and applies to arbitrary circuit components, both linear and nonlinear. By application of a stochastic Galerkin method, the stochastic problem is cast in terms of an augmented set of deterministic constitutive equations relating the voltage and current spectral coefficients. These new equations are given a circuit interpretation in terms of equivalent models that can be readily implemented in SPICE-type simulators, as such allowing to take full advantage of existing algorithms and available built-in models for complex devices, like diodes and MOSFETs. The pertinent statistical information of the entire nonlinear network is retrieved via a single simulation. This approach is both accurate and efficient with respect to traditional techniques, such as Monte Carlo sampling. Application examples, including the analysis of a diode rectifier, a CMOS logic gate and a low-noise amplifier, validate the methodology and conclude the paper.
This paper presents an all-digital, non-coherent, pulsed-UWB transmitter. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB ...pulses from an energy-efficient, single-ended digital ring oscillator. Dual capacitively coupled digital power amplifiers (PAs) are used in tandem to attenuate low frequency content typically associated with single-ended digital circuits driving single-ended antennas. Furthermore, four level digital pulse shaping is employed to attenuate RF sidelobes, resulting in FCC compliant operation in the 3.5, 4.0, and 4.5 GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90 nm CMOS process and occupies a core area of 0.07 mm 2 . The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5 pJ/pulse at data rates up to 15.6 Mb/s.
This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely ...adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 2 7 -1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER <; 10 -12 while consuming a total power of 655 mW.
The DC circuit breaker is an indispensable building block for DC network systems. Hybrid circuit breakers that combine mechanical and solid-state switches have more potential to be utilized in DC ...distribution networks because of their lower conduction losses and fast interrupt speed. The efficient energy DC interrupter with surge protection (EDISON) removes any solid-state circuit in the main current path, thereby substantially reducing the conduction losses during normal operations. However, it requires a dedicated control with fast dynamics because any false triggering of the mechanical switch or solid-state switches of the breaker would lead to a commutation failure and a potential unquenchable arc. This paper proposes a finite-state-machine (FSM) based control scheme that guarantees an accurate and fast control response during a fault event. Due to this fast response requirement, a dual-core-CPU-based control architecture is applied featuring parallel taskings and negligible communication delays between the two cores. Furthermore, a control-law-accelerator (CLA) is employed to further reduce the latency of the program execution by 33%. The controller hardware-in-the-loop (CHIL) model of the EDISON breaker is implemented in OPAL-RT to verify the control scheme and de-risk the prototype test. A fifth-order RLC network is developed to characterize the mechanical switch behavior such that the hybrid circuit model can be simulated in the CHIL solely by circuit components. Finally, the proposed control scheme is implemented and validated in a prototype test with a 3 kA interrupting current and a 60 A/μs current commutation rate.
Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new ...approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about <inline-formula> <tex-math notation="LaTeX">580 \times </tex-math></inline-formula> faster than the global MET-based method.
This paper proposes an enhanced sensorless vector control strategy using the predictive deadbeat algorithm for a direct-driven permanent magnet synchronous generator (PMSG). To derive favorable ...sensorless control performances, an enhanced predictive deadbeat algorithm is proposed. First, the estimated back electromotive force (EMF), corrected by a cascade compensator, was put into a deadbeat controller in order to improve the system stability, while realize the null-error tracking of the stator current at the same time. Subsequently, an advance prediction of the stator current based on the Luenberger algorithm was used to compensate the one-step-delay caused by digital control. Maintaining the system stability, parameters of the controller were optimized based on discrete models in order to improve the dynamic responses and robustness against changes in generator parameters. In such cases, the proposed methodology of synchronous rotating frame phase lock loop (SRF-PLL), which applies the estimated back EMF, can observe the rotor position angle and speed without encoders, realizing the flux orientation and speed feedback regulation. Finally, the simulation and experimental results, based on a 10-kW PMSG-based direct-driven power generation system, are both shown to verify the effectiveness and feasibility of the proposed sensorless vector control strategy.
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